Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> hmc routing done, guess that means I need the clock buffers now
<Lofty> "hmc"?
<Lofty> Sarayan: ^
<Lofty> You're getting through this really quickly, wow
<Lofty> ~~probably because I'm not distracting you with questions~~
<Sarayan> hard memory controller
<Sarayan> half of the i/o goes through it
<Sarayan> because it needs a fuckload of pins in the irst place