Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> downloading 9.1, thank
<Sarayan> looks like I have the pram right now, weee
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<rombik_su> Sarayan: Poke me when you're done with 9.1
<Sarayan> I am, thanks
<Sarayan> Interestingly, it already was ddb
<Sarayan> and _asm
<Lofty> Hi Sarayan and rombik_su
<mmicko> hmm, created new project with quartus.ini with PDB_ASCII_DUMP=on for CycloneII and started build, it dumps some info on console, but then it get stuck and stays at 100% CPU usage no new files generated (note this is version 13.0sp1)
<Lofty> That "getting stuck on 100% CPU usage" is a good sign, I think
<mmicko> ok, tried with dev_dump_part_data=on and that worked quite fast generting new files :)
<Lofty> mmicko: sure, but they're the unimportant ones :P
<Sarayan> mmicko: quartus_asm generates gigantic files (tens of GBs)
<Sarayan> and the files are generated in the quartus installation, in common/devinfo/*
<mmicko> quartus/common/devinfo/cycloneii/ddb_cycloneii_family.txt
<mmicko> quartus/common/devinfo/cycloneii/ddb_cycloneii_parts.txt
<mmicko> so far those two generated just fine, with PDB it is running for 10 min so far without any new file generated
<Sarayan> what's pdb?
<mmicko> PDB_ASCII_DUMP=on
<Sarayan> ah
<mmicko> I get first over 10 MB text output on start and then it goes to 100% and stays that way, but do not see any file generated
<Sarayan> where did yo ulook?
<Sarayan> and which tool are you running exactly?
<mmicko> quartus/common/devinfo/cycloneii in particular, but no changes anywhere in quartus tree
<mmicko> running quartus 13.0sp1
<mmicko> quartus_sh --flow compile test_cyclone2.qpf
<Sarayan> so you're probably in quartus_asm then
<Lofty> mmicko: yeah, it's generally much better to run the commands individually :P
<mmicko> ok will try one by one
<Lofty> map, fit, sta, asm
<Sarayan> check into common/devinfo, you should already have a bunch of .ddb.dmp files
<Lofty> rombik_su: poke
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<mmicko> ok will need to investigate 13.0sp1 but can confirm working fine with 17.0
<Lofty> The Arria V family is weird
<Lofty> The non-GZ dies look a lot like Cyclone V
<Lofty> ... Is the 5AGZ family from the Stratix V?
<daveshah> Intel seem somewhat unique in substantially changing things around within a family
<daveshah> a bit like the two totally different Cyclone 10s
<Lofty> Yeah, I'm pretty sure the 10 GX/LP is marketing
<daveshah> I mean Lattice have kind of started this too with the CrossLink-NX/Certus-NX shenanigans (same die, different bondout for different applications)
<rombik_su> Lofty: > Arria V GZ is a leftover from Stratix V, apparently:
<rombik_su> ls arriavgz: stratixv_gsf2c stratixv_gsf2d
<Lofty> Hahaha
<rombik_su> (and the whole floor sweepings deep fried joke from yesterday)
<daveshah> do we know if they are locking out regions of the device that might actually be broken, or just limiting total resource count?
<daveshah> i guess there might be speed/transceiver binning going on, too
<Lofty> I have no idea, but I guess we'll find out!
<rombik_su> I've heard from someone on twitter that static current is the same for all devices, sharing the same die and looks like those regions just being bypassed and not powered down.
<daveshah> What Xilinx do is just limit resource count
<mwk> Lofty: it's pretty obvious Arria V GZ is Stratix V and non-GZ is Cyclone V
<daveshah> This means you get a higher routing to LUT ratio than would normally be possible on the limited devices
<Lofty> mwk: or else that Cyclone V is non-GZ
<mwk> btw for xilinx ultrascale+, kintex is just zynq with ARM turned off :(
<mwk> *:)
<mwk> spartan 7 is artix 7 with disabled transceivers, etc
<mwk> (some of them anyway)
<mwk> Lofty: either way
<rombik_su> daveshah: So they somehow 'spread' inactive LUTs across the matrix?
<daveshah> there are no 'inactive' LUTs
<mwk> I got list somewhere
<daveshah> just a post-synthesis check on the total number of LUTs
<Lofty> I'm guessing that makes Kintex cheaper than Zynq because Xilinx think people can't unlock the chip?
<daveshah> the bondout is different
<daveshah> so you aren't going to unlock the chip without wirebonding equipment
<mwk> also arria gx is stratix ii gx; arria ii gx/gz is stratix iv
<mwk> also I couldn't find any major differences between cyclone 10 gx and arria 10
<mwk> Lofty: pinout is different, so you cannot touch the ARM pins
<mwk> also... you know, some people *want* an fpga without ARM?
<mwk> dunno
<daveshah> yeah I don't think the pricing is actually that different
<Lofty> mwk: I ended up making a die/model to SKU list on the mistral wiki
<mwk> also it's not wirebonded, it involves flip-chip packaging with an interposer
<mwk> which... tbh I wouldn't know how to deal with that
<rombik_su> mwk: I was amazed that Xilinx actually figure out how to make single die for both wirebond and flip-chip packages, check this out: https://siliconpr0n.org/map/xilinx/xc7a35t/mz_mit20x/#x=4856&y=1019&z=4
<mwk> yea I know
<mwk> it's right there in the datasheet :p
<Sarayan> I suspect what can tell you what is close and what isn't is the structure of the LABs
<Sarayan> f.i. 10lp and V is very different, 10lp is much simpler
<daveshah> 10lp is a totally different generation
<daveshah> same as cyc3 even afaik
<daveshah> same IDCODEs too I think
<mwk> not exactly
<mwk> hmm, or wait, maybe even exactly
<mwk> nvm, got a bit confused
<mwk> yeah, wouldn't be surprised if cyclone iii / cyclone iv / cyclone 10lp were all one and the same
<daveshah> what's confusing is that there was a notional die shrink between iii and iv
<mwk> huh, was there?
<mwk> my notes have both at 60nm
<mwk> and 10lp at [NO DATA]
<daveshah> I feel like I saw 10lp advertised as being 50-something nm
<daveshah> but maybe I'm getting things mudded
<daveshah> *muddled
<daveshah> yeah, still 60nm, nvm
<mwk> right, that stronly implies "same shit different label"
<Sarayan> V is 26nm
<Sarayan> 28nm sorry
<daveshah> no wait, cyclone iii is 65nm according to some stuff
<daveshah> all these things are a bit notional, so maybe the process was just renamed to 60nm at some point
<mwk> 65 vs 60 doesn't sound like a jump worthy of redesigning stuff
<daveshah> no, I think it might just be a marketing change at some point
<daveshah> given they didn't even bother changing the JTAG ID
<mwk> right
<mwk> wut, so cyc3... is both
<daveshah> I guess they may never have actually redesigned it, just moved to a marginally newer process
<mwk> right
<rombik_su> I had to work with a device with 9 C4/S4 FPGAs in the same JTAG chain and it was so nice clicking through those 'select your device' pop-ups
<daveshah> yeah, I remember that back playing with C3 too, although I didn't have a chain of them...
<daveshah> heh, seems like the magic scale factor changed at some point too because the largest Cyc IV E is 114k LE and the largest 10 LP is 120k LE but other parameters look the same
<rombik_su> Looks like there's a significant drop of NRE and per-die manufacturing cost every 3-4 years. We did the full-mask in 40LP TSMC 2 years ago, now you can do 28HPC+ roughly for the same money.
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