04:08 <omnitechnomancer> Does the Cyclone V have DMA access to the hardproc RAM from the FPGA?

09:42 <Sarayan> i think all dmas have to be setup from the hps side

09:44 <Sarayan> but the fpga2hps block looks like it may have direct ram access

09:45 <Sarayan> plus the boot-from-fpga mechanism allows the fpga ti fill the internal ram then boot the cores from there

09:45 <Sarayan> so yes, but not through the dma subsystem

09:49 <omnitechnomancer> Well by DMA I mean being able to read and write the HPS RAM

10:05 <Lofty> omnitechnomancer: they share the DDR3 memory controller

10:14 <omnitechnomancer> Cool

10:14 <omnitechnomancer> Might get a DE10-Nano at some point

10:45 <Lofty> That's going to end up the first supported board at this point

10:46 <omnitechnomancer> \o/

10:46 <omnitechnomancer> Does Altera list LE numbers in the same fudged way as everyone else?

10:47 <Lofty> Yeah..

10:48 <omnitechnomancer> annoying

10:48 <Lofty> Your magic number here is 2.5

10:48 <Lofty> 2.5 LEs to an ALM.

10:59 <omnitechnomancer> so the 110kLE of the DE10's FPGA is more like 44k ALMs?

11:06 <Sarayan> Lofty, do you know how to instanciate m10ks, dsps and even mlabs in memory mode in quartus?

11:08 <Lofty> - cyclonev_ram_block

11:08 <Lofty> - cyclonev_mac

11:08 <Lofty> - cyclonev_mlab_cell

11:13 <Sarayan> nice

11:14 <Sarayan> I suck at verilog, could you build some examples that just do that, instanciate such a cell and route inputs/outputs/clocks on pins?

11:16 <Sarayan> It's 4191 LABs or MLABs, each including 10 lut6 or 20 lut5 and 40 FF

11:28 <omnitechnomancer> clearly write the examples in VHDL instead :P

11:50 <Sarayan> I was doing vhdl 20 years ago, I've forgotten so much :-)

11:51 <Sarayan> also 112 dsp and 553 m10k fwiw

11:52 <omnitechnomancer> I first learned VHDL but have not done any in a long time

11:53 <Sarayan> nmigen forever :-)

11:56 <Lofty> Sarayan: https://github.com/YosysHQ/yosys/blob/master/techlibs/intel_alm/common/quartus_rename.v

11:56 <omnitechnomancer> I need to learn nmigen

12:49 <Sarayan> nice, thanks

18:03 <chipb> regarding the fpga to ddr access, iirc they can indeed share the same hard memory controller, but there's an ability to drive a ddr solely from the fabric side. I recall the reference design for the terasic cyclone v devkit (the one retailing for 1.5K? USD) includes a dedicated ddr for fpga design use.

18:04 <chipb> I can't recall if it's a soft controller or not though.

18:05 <chipb> ahem. s/devkit/soc &/

18:07 <Sarayan> there are two hardware memory controllers in the sx120f, one on the fpga side and one on the hps side

18:08 <Sarayan> same for the sx50f

18:08 <Sarayan> e50f and gx25f have only one hmc, gt* has two

18:25 <chipb> yeah, that seems familiar. been quite some time since I was working with the cyclone parts.

20:37 <Lofty> Sarayan: I really need you to teach me how the hardware works; I feel like a shitty project lead for not knowing how things work.

21:45 <Sarayan> need to write a doc, it will be needed

22:14 <omnitechnomancer> Secret of hardware: It doesn't work

22:24 <chipb> Corollary of it working: Bodge a workaround in software