Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Lofty: The idea about mistral-cyclonev is to move everything that can be public into mistral itself once we feel like it
<Sarayan> e.g. idata, itools, notes can't be public, the rest can be
<Sarayan> I kinda follow the EU rule of "minimum public data for interoperability"
<Sarayan> e.g. what will be public will be facts needed to actually do the work
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<Lofty> Mmm
<Sarayan> two more block types, wee
<Sarayan> Need to map the fpll boundaries though
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<Sarayan> that will solve a lot of stuff
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<Sarayan> wow, the fpll have a register r/w interface with 6 bits of address and 16 bits of data
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<Lofty> Huh.
<Sarayan> I guess it's standard for the from-cpu control
<daveshah> Yeah thats pretty common, Xilinx and some Lattice have that too
<daveshah> iCE40 unusually has a serial shift register reconfig interface for the PLL
<Sarayan> cute
<mwk> ... Spartan 6 has shift register for the DCM too
<mwk> because why not both
<daveshah> Ran out of wires for a parallel interface?
<mwk> more like they repurposed an old interface for phase control
<mwk> which only had "go up" and "go down" commands
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