Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Lofty: Yes, but otoh if someone wants to do a native Rust version it's way easier
<Sarayan> 99% of the information is in data with the python code in tools generating c++ from it
<Sarayan> There is some hardcoded stuff, like the patterns, mostlt for historical reasons
<Sarayan> and iirc there's some name conversions I do in tools I should do earlier, to be fixed later again
<awygle> a native rust version of what?
<Sarayan> the cyclone v firmware compiler/decompiler/general info library
<Sarayan> It's not interesting to convert it to anything at that point, since it's getting massive revisions every couple of day, being in intense RE mode still, but eventually...
<awygle> ah
<Sarayan> there's stuff that directly comes for quartus that we shouldn't make public, but the results which are afaict only dependent on the fpga itself we will, hopefully soon
<awygle> cool
<Sarayan> a bit like a clean room implementation 'cept the room is not really clean. More along the lines of the EU policy of "make public only the needed information for interop", which I interpret as the information needed to work with the cyclonev fully independently of quartus
<Sarayan> but not helping people interested into looking into quartus for some reason, because it's not interop with quartus I'm interested in
<awygle> right
<Sarayan> iow following the spirit of the EU RE rules to the best of my ability
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