Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> People, what could "DLL" expand to to mean something around digital delay line?
<Sarayan> Maybe it's DeLay Line mind you
<Sarayan> oh no, it's a delay-locked-loop
<Sarayan> since there's a locked output
<daveshah> They are commonly used around IO for things like 90 degree phase shifted sampling
<Sarayan> it's used between a pll and a dqs
<Sarayan> for the sdram/ddr/etc interfaces
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