Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<chipb> Sarayan: er. what chip are you talking about? because while I understand the theoretical PR capability/signals may be there, it's specifically unsupported on cyclone v for more than just marketing reasons.
<chipb> oh, and the bag of opaque bits for hps interface is a dumpster fire even for people willing to work with quartus.
<chipb> pretty irritating how you must create a qsys system to do anything to configure it.
<chipb> also: mwk++; do not recommend.
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<Sarayan> chipb: the whole cyclone v series, and in particular the 5CSEBA6U23I7 of the mistral
<Sarayan> aka sx120f
<Sarayan> or se120b
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<Sarayan> oh, I've found the table that "explains" the 3173 SIMPLE_RPI bits
<Lofty> Sarayan: excellent
<chipb> well, thar be dragons. be aware you may see unreliable behavior even once you're drive the signals correctly. :-(
<chipb> unless something changed with those parts in recent years.
<Lofty> Well, that's the point of a documentation project: to document even the bugs :P
<chipb> oh, fair enough.
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