<tpb>
Title: [Temporary] v2x stuff to merge - Google Docs (at docs.google.com)
<sf-slack2>
<kgugala> I think @mkurc should also take a look on this doc
<sf-slack2>
<mkurc> @kgugala Looking...
<sf-slack2>
<acomodi> litghost: one question, now that the split is on, is the `specialize carrychain` still required?
<litghost>
acomodi: Good question. I don't know
<litghost>
acomodi: I think this is a case where without timing information, it is hard to evaluate the quality of output before and after
<litghost>
acomodi: I recommend we focus on getting equivilant tiles landed, and timing
<litghost>
acomodi: And after that, we can evaluate specialize vs no specialize and round robin vs no round robin
<litghost>
acomodi: I think letting result quality be our guide once we have results will help make descisions
<sf-slack2>
<acomodi> litghost: Agreed, it just popped up in my mind. For sure it is something that can be postponed
<litghost>
acomodi: Let's make sure an issue is tracking the idea
<sf-slack2>
<acomodi> litghost: I'm on it
<litghost>
acomodi: Oh, okay
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<mithro>
kgugala / mkurc: For now I think in v2x / sim.v files I think we should use explicit mux specification rather than implicit mux inference
<sf-slack2>
<kgugala> @mithro I agree
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<mithro>
kgugala / mkurc: I added a quick section at the top on how I think we should handle all the things
<hackerfoo>
I noticed read_uart.py is discarding some data, since it just reads 10KB at a time. Is it worth making read_uart.py and error_output_logic.v more robust?
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<hackerfoo>
(in arch-defs/xc7/tests/common)
<litghost>
hackerfoo: Yes/no. I'd start with just adding the RAM32M test, and then maybe as a follow up improving error_output_logic.v
<hackerfoo>
litghost: Okay, agreed.
<hackerfoo>
Has ERROR_OUTPUT_LOGIC.DATA_WIDTH(2) been tested? I'm getting 'E' right now, but read_uart.py doesn't seem to parse it because it doesn't print anything, it just happily munches all the data.
<litghost>
hackerfoo: No, but I believe DATA_WIDTH(16) is being used with BRAM
<litghost>
and DATA_WIDTH(32) I believe?
<hackerfoo>
Yes, in bram_sdp_test. Hmm.
<litghost>
hackerfoo: I recommend starting with
<litghost>
xxd /dev/ttyUSBX
<litghost>
stty raw 500000 < /dev/ttyUSBX
<litghost>
hackerfoo: Or redirect to a file and use xxd
<hackerfoo>
Yeah, I did that. That works, and I get 'E'', so I didn't want to manually parse the results to debug it.
<hackerfoo>
I'm tempted to make error_output_logic.v dump ASCII hex over the UART.
<hackerfoo>
And end records with \n.
<hackerfoo>
Anyway, I should just fix read_uart.py
<litghost>
hackerfoo: I avoided bin -> ASCII because I wanted to keep resource utilization low
<litghost>
hackerfoo: But because we are fairly stable for the combintorial elements, it's probably safe
<litghost>
hackerfoo: Just make sure the bin -> ASCII is implemented as combintorial elements, and not another LUT-RAM
<hackerfoo>
Okay
<hackerfoo>
Should just be shifting and '0' + data[3:0]
<hackerfoo>
Ah, not for A-F.
<litghost>
hackerfoo: Exactly
<litghost>
hackerfoo: You should output ASCII octal
<litghost>
could*
<litghost>
hackerfoo: FYI 9-scalable proc does bin -> hex
<hackerfoo>
I find hex a lot easier to read.
<hackerfoo>
Hopefully a branch for 0-9 and A-F shouldn't be too bad.
<hackerfoo>
Ah, scalable_proc uses a case statement. I'll have to try that. It probably gets synthesized as a LUT.
<litghost>
acomodi: That is an improvement of 16 minutes, so it isn't nothing
<sf-slack2>
<acomodi> litghost: well, if put in percentage it's a ~19% improvement which looks much better. let me rephrase: it is a good improvement :slightly_smiling_face:
<hackerfoo>
Is it bad practice to leave inputs disconnected in Verilog if they don't matter? I know it's not good to let inputs float.
<hackerfoo>
And if so, is it better to set them high than low?
<litghost>
hackerfoo: Disconnected is fine if they are truly don't care
<litghost>
hackerfoo: The hardware will always set them to something stable