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<litghost> hackerfoo: If the high address lines are tied high, than it is two independent RAM18E1, if tied to signals one RAM36E1
<litghost> hackerfoo: I don't have a good mental model of how this all works out
<hackerfoo> That's similar to how tying A6 high keeps O5/O6 independent for two DPRAM32s.
<hackerfoo> Once I get the 36k block working, I'll try drawing some schematics.
<litghost> hackerfoo: If the scheme is the same as DPRAMs, that implies interesting things about the data ports which I don't think is supported by the routing. It'll be interesting to see the schematics
<litghost> hackerfoo: Read data ports specifically
<hackerfoo> Any idea why is RSTRAMARSTRAML called RSTRAMARSTRAMLRST in the db? It's RSTRAMARSTRAML in Vivado as expected.
<litghost> Link?
<tpb> Title: symbiflow-arch-defs/bram.pb_type.xml at dba00415ae607c6b5768c4c3c0d2626839ecc702 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost> That should match a wire name
<litghost> Check the name of the wire, rather than the port name
<litghost> Could just be a typo!
<litghost> I just checked, and the wire does not have that last RST
<hackerfoo> How do I fix it?
<litghost> Presumably that wire was never getting connected at the top level pb, so just rename the port :)
<litghost> Interesting, I just check the generated top level pb, and it does have the post-fix
<litghost> :/
<litghost> Ah, I was look at the wrong wire
<litghost> You might have been too
<hackerfoo> I guess I'll just do a global search-and-replace, but it's probably somewhere in prjxray that generates the db.
<litghost> RSTRAMARSTRAMLRST != RSTREGARSTREGL
<litghost> RSTRAMARSTRAMLRST is the correct wire name
<litghost> The current port name is correct
<litghost> To show it in vivado run:
<litghost> select_objects [get_nodes BRAM_L_X6Y135/BRAM_FIFO36_RSTRAMARSTRAMLRST]
<litghost> So sorry for the confusion, but the port is actually named correctly
<hackerfoo> Then where is RSTRAMARSTRAML?
* hackerfoo uploaded an image: Screenshot from 2019-05-14 18-16-06.png (8KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/KdHMKXNBcWXHvDxBdPFovxAN >
<hackerfoo> Right under RSTRAMARSTRAMU
<hackerfoo> This is my design just using Vivado.
<hackerfoo> Also, it follows the U/L naming scheme for inputs into the two halves of the RAMB36E1.
<hackerfoo> I'm pretty sure it's a typo.
<hackerfoo> I blame Xilinx for their ridiculous names.
<litghost> hackerfoo: Oh, you are looking at the block in RAM36E1 mode
<litghost> hackerfoo: Click the wire itself, and it will have the RST postfix
<litghost> hackerfoo: And if you check a block in "RAMBFIFO36E1 (primary)" you'll see the port name change
<litghost> hackerfoo: Super fun
<hackerfoo> Can you send a screenshot? I only have GLOBAL_LOGIC1
* hackerfoo uploaded an image: Screenshot from 2019-05-14 18-32-55.png (6KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/mXVWFGnvozPKDaxDFvKGAdxG >
<mithro> duck2's first contribution as part of GSoC! https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/51
<tpb> Title: Enable PugiXML compact mode by duck2 · Pull Request #51 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com)
<duck2> yay :P the sax reader was much bigger, but the fastest sax parser is 3x slower than pugixml, so it kind of failed.
<litghost> hackerfoo: You are selecting the net, not the wire or node
<litghost> hackerfoo: Click again and it will select the node and then the wire
<hackerfoo> Okay, I'm pretty sure that's a typo on Vivado's end:
* hackerfoo uploaded an image: Screenshot from 2019-05-14 19-51-49.png (16KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/PavprCKUBzETmGxgiIrELcOK >
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<hackerfoo> litghost: Should we copy Vivado's typos?
<litghost> hackerfoo: Yes
<litghost> hackerfoo: Because it isn't a typo
<hackerfoo> Why? What does it mean?
<litghost> hackerfoo: The way to read it is "RSTRAMA | RSTRAML | RST"
<hackerfoo> The U pin doesn't have the RST suffix.
<litghost> hackerfoo: Flip through the 3 modes of the RAMB36E1 and you will see why
<litghost> hackerfoo: Actually the way to read it is "RSTRAMARSTRAML (RAMB36E1) | RST (FIFO36E1)"
<hackerfoo> Ah. Why can't they use an underscore or something?
<hackerfoo> litghost: Is there an easy way to flip through the modes?
<litghost> hackerfoo: Just select an unselected BRAM36E1 cell, and then select the type in site properties window
<hackerfoo> litghost: Thanks
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<sf-slack2> <acomodi> litghost: I would need some feedback on my comment of this issue: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/513#issuecomment-492225837. Does it sound correct?
<tpb> Title: Support Equivalent Placement Sites · Issue #513 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)
<sf-slack2> <acomodi> litghost: mainly because I believe that the change described in the comment requires a moderate amount of effort
<litghost> acomodi: Sorry, can you provide more context?
<litghost> acomodi: I haven't seen a comment from the VTR dev's since 27 days ago
<litghost> acomodi: Why not have them first look at the implementation you have done, and evaluate it
<litghost> acomodi: Rather than preemptively conforming to another design
<sf-slack2> <acomodi> litghost: Ok, makes sense, I wanted to explore other possible designs and see if they were implementable.
<sf-slack2> <acomodi> litghost: in the meanwhile though I am stalled until there is a preliminary evaluation. What do you think could I focus on?
<litghost> acomodi: If you think the suggestion in the issue is worth pursuing I won't stop you, but my understanding is we have an implementation that works. How do the performance before/after numbers look?
<litghost> acomodi: I would suggest ROI breakout work, e.g. VPR tiles for the clock column and IOB's
<sf-slack2> <acomodi> litghost: ok first I will get some reports (e.g. run_time and placement cost), but I can extract those only from Symbiflow xc7 tests as equivalent tiles is supported only by those right now
<litghost> acomodi: Oh, you need to write the arch top-level pb_type to tiles tool
<litghost> acomodi: Did that happen?
<litghost> acomodi: Because you should be able to run against the full suite through the tool, yes?
<sf-slack2> <acomodi> litghost: you mean VTR test suite or the symbiflow one?
<litghost> acomodi: VTR test suite
<sf-slack2> <acomodi> litghost: anyway there is an initial PR with a script that moves the top level pb_types to the tiles tag (without adding the equivalent tiles though) https://github.com/SymbiFlow/symbiflow-arch-defs/pull/583
<tpb> Title: WIP: added script to add tiles tag and equivalent tiles by acomodi · Pull Request #583 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost> acomodi: But I believe there was agreement that script needed to live in VPR?
<litghost> acomodi: Unless your PR allows old style arch-xml's to work as is?
<litghost> acomodi: I thought your PR required the new style tiles definition?
<sf-slack2> <acomodi> litghost: No, the script is needed as the pb_type cannot have some child tags anymore (e.g. fc, pinlocations, ...)
<litghost> acomodi: I think we agree that the script is needed, and it should be a part of VPR because anyone using VPR would be affected
<litghost> acomodi: Not just symbiflow
<sf-slack2> <acomodi> litghost: Yes indeed, in fact I do believe that it will take a while before the PR will get merged as it introduces a great change in the whole architecture definition
<sf-slack2> <acomodi> litghost: I will add the script to VPR then
<litghost> acomodi: I think discussing that point directly with the VTR devs is worth doing
<sf-slack2> <acomodi> litghost: to make CI green on VPR and be able to test on all the architectures
<litghost> acomodi: Yes
<litghost> acomodi: There is an open question in my mind if VTR should do the top level pb_type to tile conversion internally to avoid requiring a format change
<litghost> acomodi: But I'll let the VTR devs drive that choice
<sf-slack2> <acomodi> litghost: you mean change all the architectures to be compliant with the new tiles concept instead of using a script at runtime?
<litghost> acomodi: As a fallback, or something
<litghost> acomodi: Or maybe a config flag
<litghost> acomodi: I haven't thought my about this, I'm just trying to explore other avenues to avoid required a lot of action for endusers of VPR
<litghost> much*
<litghost> acomodi: Overall, I would let the VRP devs guide the conversion on the breaking of backwards capability
<sf-slack2> <acomodi> litghost: Makes sense. In fact, for now it is better to rely on a script, but it surely is something to discuss with VPR devs as you said
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<mithro> elms: If you are okay with it, O
<mithro> bah
<mithro> elms: If you are okay with it, I'll merge https://github.com/SymbiFlow/symbiflow-arch-defs/pull/731
<tpb> Title: travis: Enable running scripts locally. by mithro · Pull Request #731 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<elms> mithro: LGTM
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<mithro> acomodi: my preference is that we have a script which can do the conversion and only support the new format directly
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