00:21 <litghost> hackerfoo: That is a suprising behavior

00:21 <litghost> hackerfoo: Sounds like we have a bug somewhere

00:25 <mithro> acomodi: I fixed up that document

09:09 <sf-slack2> <acomodi> mithro: Great, thanks

13:54 <litghost> acomodi: Did https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a9571799679e188c9b91f1fbbde3856ae48f08d0 make it to our downstream VTR fork?

13:54 <tpb> Title: mode selection: small fixes · verilog-to-routing/vtr-verilog-to-routing@a957179 · GitHub (at github.com)

13:55 <sf-slack2> <acomodi> litghost: Not yet, I'll apply them now

13:56 <sf-slack2> <acomodi> litghost: sorry, no those are not included in our master+wip

13:56 <litghost> acomodi: That's okay, the priority is getting the mode selection fixes upstream

13:57 <sf-slack2> <acomodi> litghost: yep, I have noticed that the regression tests are extremely sensitive

13:59 <sf-slack2> <acomodi> litghost: anyway I think that now everything is ok, titan benchmarks returned with very good QoRs, packing time is still even with the master

14:07 <sf-slack2> <mkurc> I added support for importing SDF timings to V2X. https://github.com/SymbiFlow/symbiflow-arch-defs/pull/765

14:07 <tpb> Title: Support for SDF timing import for V2X by mkurc-ant · Pull Request #765 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

14:54 <sf-slack2> <kgugala> @mithro can we bump the database so it has the latest sdfs? There were quite a few fixes merged in https://github.com/SymbiFlow/prjxray/commit/8cb7366fa2c361fd5c8eec0aa0cb976808a39752

14:54 <tpb> Title: Merge pull request #835 from antmicro/bel-timings-fixes · SymbiFlow/prjxray@8cb7366 · GitHub (at github.com)

15:32 <sf-slack2> <acomodi> litghost, mithro: https://docs.google.com/document/d/11hlBnzs_1SfzWTVxWYQNDCDxRJFroodoIORaDiWbylw which of the commits marked as workarounds are likely to be pushed upstream in your opinion?

15:32 <tpb> Title: SymbiFlow VtR Status - Google Docs (at docs.google.com)

16:39 <mithro> hackerfoo: https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/xc7/libraries

16:39 <tpb> Title: symbiflow-arch-defs/xc7/libraries at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

16:48 <mithro> acomodi: https://github.com/mithro/vtr-verilog-to-routing/tree/port_bit_name

16:48 <tpb> Title: GitHub - mithro/vtr-verilog-to-routing at port_bit_name (at github.com)

17:44 <mithro> mkurc: It'll take me a while to digest what your doing with the SDF loading in v2x...

17:59 <sf-slack2> <mkurc> @mitrho: I've seen your comment. So you wanted to have a flow like SDF -> Verilog -> XML ?

18:00 <sf-slack2> <mkurc> Or to update JSON generated by Yosys with timings from SDF ?

22:05 <hackerfoo> read_uart.py doesn't seem to work any more on master with dram_test or bram_test

22:06 <hackerfoo> The serial data looks fine at 500000 baud.

22:10 <hackerfoo> I don't see any recent changes, though. It must be a dependency.

22:47 <hackerfoo> The result format got a byte shorter.

23:22 <litghost> hackerfoo: Also possible that it is a regression

23:39 <hackerfoo> I can't find any changes to the logic. It seems that the loop count is only one byte, even though the state machine should output two bytes. The header, CR, LF are all there, and the error count is 0.

23:40 <hackerfoo> The loop count seems to be going down, but that could just be aliasing.

23:49 <litghost> hackerfoo: You looking at simulation?

23:50 <hackerfoo> I tried autosim. It just showed running clocks but the other waveforms were flat.

23:53 <hackerfoo> I suppose I should try bit2v in Vivado