<mithro> mkurc: Looks like we missed attributes on port connections....
<mithro> See my further comments on https://github.com/SymbiFlow/yosys/pull/25
<tpb> Title: Support for attributes on parameters in Verilog by mkurc-ant · Pull Request #25 · SymbiFlow/yosys · GitHub (at github.com)
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<sf-slack2> <mkurc> @mithro: You are right. I created an issue to track remaining attribute use cases in Yosys: https://github.com/SymbiFlow/yosys/issues/27. I will be updating this today.
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<sf-slack2> <mkurc> @litghost: I filed an issue regarding my concerns about modeling FDCE with timings: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/788
<tpb> Title: Modeling the FDCE with timing for VPR · Issue #788 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack2> <kgugala> @litghost dff split PR https://github.com/SymbiFlow/symbiflow-arch-defs/pull/789
<tpb> Title: xc7: dff: split dff into {FF|REG}_INIT and update timings by kgugala · Pull Request #789 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
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<hackerfoo> mithro: Yeah - I'll review it now.
<hackerfoo> Ah, that was left over from before O5/O6 were split, I think.
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<tpb> Title: Remodel RAM as dual-port fracturable by HackerFoo · Pull Request #663 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
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