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<sf-slack>
<p.vanleeuwen> Hey there! I'm working on my graduation thesis (CS) in which I analyse FPGA emulation (specifically, the ECP5). For this, it would be very helpful to have a graph/network model of an FPGA. The Trellis project collected the information that I need, but I can't seem to find how to extract the (connectedness) information from this project. The JSON files are only machine-readable and the HTML documentation seems
<sf-slack>
sparse as well (I have no background in hardware / FPGAs). Can anyone recommend me how to obtain this connectedness information / graph model? Any help would be greatly appreciated:D Best regards, Pim
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<ZirconiumX>
daveshah ^
<daveshah>
p.vanleeuwen: If you look in the per-tile databases, all the connections are there