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<sf-slack> <p.vanleeuwen> Hey there! I'm working on my graduation thesis (CS) in which I analyse FPGA emulation (specifically, the ECP5). For this, it would be very helpful to have a graph/network model of an FPGA. The Trellis project collected the information that I need, but I can't seem to find how to extract the (connectedness) information from this project. The JSON files are only machine-readable and the HTML documentation seems
<sf-slack> sparse as well (I have no background in hardware / FPGAs). Can anyone recommend me how to obtain this connectedness information / graph model? Any help would be greatly appreciated:D Best regards, Pim
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<ZirconiumX> daveshah ^
<daveshah> p.vanleeuwen: If you look in the per-tile databases, all the connections are there
<tpb> Title: prjtrellis-db/bits.db at master · SymbiFlow/prjtrellis-db · GitHub (at github.com)
<daveshah> .mux is for programmable connections, and .fixed_conn <dst> <src> for fixed connections
<daveshah> There's a normalisation scheme, so E3_ for example is a reference to a named wire in the grid location 3 to the east
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<hackerfoo> I added some documentation for my VTR testing Nix configuration: https://github.com/HackerFoo/vtr-nix-test
<tpb> Title: GitHub - HackerFoo/vtr-nix-test: Using Nix to run VTR tests (at github.com)
<hackerfoo> I'm getting ready to run a sweep over `--inner_num` for `vtr_reg_weekly`.
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<_whitenotifier-3> [symbiflow-arch-defs] mithro opened issue #1394: Add version to .travis.yml file - https://git.io/JvbcY
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<_whitenotifier-3> [prjxray] mithro opened issue #1288: Add version to .travis.yml file - https://git.io/JvbcG
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<sf-slack> <timo.callahan> Hi all, is there an existing test/demo for Symbiflow + Litex/VexRiscV + Linux targeting Arty A7 35T? I know of the Vivado-based example (https://github.com/litex-hub/linux-on-litex-vexriscv), and Symbiflow+Linux on Zynq (https://github.com/antmicro/symbiflow-linux-guide), but not exactly the combination I mentioned. Thanks for any tips!
<tpb> Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)
<tpb> Title: symbiflow-arch-defs/xc/xc7/tests/soc/litex/mini_ddr at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<tpb> Title: symbiflow-arch-defs/xc/xc7/tests/soc/litex/base at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack> <timo.callahan> Thanks litghost, I'll take a look.