07:54 <FFY00> mithro, got a automated arch pkg builder example

07:54 <FFY00> it's a bit slow but it works

07:54 <FFY00> https://github.com/FFY00/symbiflow-arch-pkgs/runs/601015898?check_suite_focus=true

07:54 <tpb> Title: github: add build action · FFY00/symbiflow-arch-pkgs@fd9b1b6 · GitHub (at github.com)

07:55 <FFY00> if we choose to use this it might be worth to hosting a self-runner

07:55 <FFY00> *to host

08:03 <FFY00> well, it's failing, I think because of missing disk space :/

09:56 <_whitenotifier-3> [symbiflow-arch-defs] rakeshm75 opened issue #1431: Branch : Quicklogic : Different ports and port names in top_bit.v file compared to the design file - https://git.io/JfTvX

11:56 <_whitenotifier-3> [symbiflow-arch-defs] mkurc-ant opened issue #1432: Add support for IDDR primitives - https://git.io/JfTTn

14:49 <sf-slack> <mkurc> I've made a fix to VPR that dramatically improves placement results on Artix 200T: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1284

14:49 <tpb> Title: Placement bb cost computation fix by mkurc-ant · Pull Request #1284 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)

15:07 <mithro> daniellimws: Do you have a temporary fix to get the readthedocs generation working again?

15:08 <daniellimws> mithro: It should work if we revert the verilog-diagram extension to before adding compat-int

15:09 <_whitenotifier-3> [sphinxcontrib-verilog-diagrams] mithro opened issue #15: Add links to the git repo from readthedocs - https://git.io/JfTOf

15:09 <mithro> daniellimws: We can pin to the older version in the requirements.txt file?

15:12 <mithro> @duck2 https://github.com/duck2/uxsdcxx/issues/50

15:12 <tpb> Title: Transfer this repo to SymbiFlow organization · Issue #50 · duck2/uxsdcxx · GitHub (at github.com)

15:14 <daniellimws> mithro: Oh yes we can

15:14 <daniellimws> mithro: Shall I open a PR for that as well

15:25 <mithro> @daniellimws Yes please

15:44 <mithro> @daniellimws Looks like the memory issue is back :-/

15:45 <daniellimws> mithro: Oh boy what's that, I haven't seen that before

16:02 <daniellimws> mithro: Can this be merged? https://github.com/SymbiFlow/python-symbiflow-v2x/pull/41

16:02 <tpb> Title: Allow docs/Makefile to be portable by daniellimws · Pull Request #41 · SymbiFlow/python-symbiflow-v2x · GitHub (at github.com)

16:12 <_whitenotifier-3> [fpga-tool-perf] acomodi opened issue #70: Collect results from CI and upload as artifacts - https://git.io/JfTsq

16:24 <daniellimws> mithro: I just remembered that I didn't add the license headers to setup.py in the v2x repo. Do you think we need it there?

16:25 <mithro> daniellimws: Yes

16:28 <daniellimws> mithro: What about empty __init__.py files

16:28 <mithro> daniellimws: They can stay empty

18:57 <duck2> @mithro I get an error "You don’t have the permission to create public repositories on SymbiFlow".

19:52 <mithro> duck2: You should have an invite to join the SymbiFlow organization now

19:55 <mithro> duck2: Thanks!

19:56 <duck2> mithro: you're welcome! https://github.com/SymbiFlow/uxsdcxx

19:56 <tpb> Title: GitHub - SymbiFlow/uxsdcxx: generate C++ reader/writer from XSD schema (at github.com)

20:12 <litghost> mithro: We need to update VTR's github address to point to the new location

20:12 <litghost> https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/CMakeLists.txt#L252

20:12 <tpb> Title: vtr-verilog-to-routing/CMakeLists.txt at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)

20:12 <mithro> By "VTR's github address" what you mean for that?

20:13 <mithro> litghost: Ahh, it should be automatically redirected at the moment

20:13 <litghost> Oh, ok

23:40 <sf-slack> <haskal> prjxray question: how do the bram segbits work, particularly how do the init strings for a ramb36 correspond to init strings for the 2 component ramb18 elements?

23:43 <sf-slack> <haskal> i have a test bitstream for zynq7 that divides a 32 bit block memory space into 1 ramb36 element per bitlane, that i populated with a basic bram mem file that has 512 words of 00000001, so all the set bits go into a single one of the bram elements

23:44 <sf-slack> <haskal> i can see in the debug output of updatemem that there is a INIT_00 and INIT_01 for one of the bram elements with all bits set, as expected, however the resulting bitstream appears to have the bits set across only 2 of the frames

23:45 <sf-slack> <haskal> i had assumed the ramb18s get concatenated into the ramb36, and if this were the case it should take 4 frames for this data

23:49 <mithro> haskal: Did you see the ram patching tool?

23:49 <mithro> haskal: https://github.com/SymbiFlow/prjxray-bram-patch

23:49 <tpb> Title: GitHub - SymbiFlow/prjxray-bram-patch: Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams. (at github.com)

23:54 <litghost> haskal: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/techmap/cells_map.v#L1558-L1595

23:54 <tpb> Title: symbiflow-arch-defs/cells_map.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

23:56 <litghost> haskal: BRAM bits in prjxray document the bits as they map to BRAM18's, not to BRAM36

23:56 <litghost> haskal: BRAM36 can then be mapped on BRAM18, per the link above

23:58 <sf-slack> <haskal> i think this will be helpful, thanks everyone