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<sf-slack> <timo.callahan> @mithro , I might need permission on foss-fpga-tools-kokoro in order to use the image "opt-xilinx--2018-01-10". Or else I'm doing something else wrong. @litghost , I'm trying "gcloud compute disks create tcal-xlnx-172-disk --image-project=foss-fpga-tools-kokoro --image=opt-xilinx--2018-01-10 --zone=us-central1-a", and I get an error "The project 'foss-fpga-tools-kokoro' was not found."
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<mithro> timo.callahan: I think the project is actually called foss-fpga-tools rather than foss-fpga-tools-kokoro due to hysterical raisins
<daniellimws> mithro: I see that the documentation for python-symbiflow-v2x looks incomplete, for example https://python-symbiflow-v2x.readthedocs.io/en/latest/tests/vtr/lutff-pair.html Are they meant to be just like that?
<tpb> Title: LUT with FlipFlop Example SymbiFlow Verilog to XML (V2X) 0.0-441-g4bc9809 documentation (at python-symbiflow-v2x.readthedocs.io)
<mithro> @daniellimws It could use work
<daniellimws> I was reading about fasm https://symbiflow.readthedocs.io/projects/vtr/en/latest/utils/fasm.html . Am I right to say that fasm_mux does not generate a multiplexer in the HDL sense, like `o = s ? a : b`? But is used to decide which connection to make when generating the bitstream instead? Because the documentation states that "From the perspective of genfasm, the <direct> and <mux> tags are equivalent." which was confusing to me.
<tpb> Title: FPGA Assembly (FASM) Output Support Verilog-to-Routing 8.0.0-dev documentation (at symbiflow.readthedocs.io)
<mithro> @daniellimws https://python-symbiflow-v2x.readthedocs.io/en/latest/tests/clocks.html has some diagrams that should be included
<tpb> Title: Clock Examples SymbiFlow Verilog to XML (V2X) 0.0-441-g4bc9809 documentation (at python-symbiflow-v2x.readthedocs.io)
<mithro> daniellimws: There are two types of muxes in an FPGA, those which are controlled via the bitstream (called routing muxes) and those controlled via user signals (sometimes called BELs or Logic muxes)
<daniellimws> mithro: So routing muxes are never defined by the user? I saw some examples that used such muxes for registered ports (https://symbiflow.readthedocs.io/projects/vtr/en/latest/tutorials/arch/configurable_memory_bus.html)
<tpb> Title: Configurable Memory Bus-Based Tutorial Verilog-to-Routing 8.0.0-dev documentation (at symbiflow.readthedocs.io)
<mithro> FFY00: If your into working on tooling, I found an old doc at https://docs.google.com/document/d/1tFdp3GdU8f89IQIZC19RgkHSgObbWXd17ZLcEiDVQxg/edit
<tpb> Title: Missing random SymbiFlow tooling - Google Docs (at docs.google.com)
<mithro> daniellimws: I'm not sure what you mean by "defined"?
<mithro> daniellimws: I found this old doc which was very much a WIP -> https://docs.google.com/document/d/1ngck6LGVTXm6HDrVqWeEGdEELrKPWXVaeejkXurgfl4/edit
<tpb> Title: SymbiFlow Parts Encyclopedia - Google Docs (at docs.google.com)
<daniellimws> mithro: Because to generate a logic mux, we can define it in verilog using the `o = s ? a : b` syntax right? But is there any such syntax for routing muxes?
<mithro> s would be a constant for a routing mux
<daniellimws> Ah ok thanks, learning so many new things beyond hardware design from reading the VPR documentation/tutorials. Interesting stuff.
<daniellimws> mithro: For the missing parts in https://python-symbiflow-v2x.readthedocs.io/en/latest/tests/clocks.html should there also be verilog code? I think I can work on this
<tpb> Title: Clock Examples SymbiFlow Verilog to XML (V2X) 0.0-441-g4bc9809 documentation (at python-symbiflow-v2x.readthedocs.io)
<mithro> @daniellimws Yeap, I think so! and auto-generated diagrams
<tpb> Title: Sphinx Verilog Diagrams Sphinx Verilog 0.0-19-gdca0472 documentation (at sphinxcontrib-verilog-diagrams.readthedocs.io)
<daniellimws> Wow this looks neat. By the way, shall we change to using the readthedocs theme instead of the material theme. The things feel out of place...
<mithro> daniellimws: Hrm? We use the martial design theme for all the symbiflow docs
<tpb> Title: Primitive Block Timing Modeling Tutorial Verilog-to-Routing 8.0.0-dev documentation (at symbiflow.readthedocs.io)
<daniellimws> the vpr docs
<mithro> @daniellimws That looks like a bug, it should be rendered with the material design theme. Can you log an issue against https://github.com/SymbiFlow/symbiflow-docs repo?
<tpb> Title: GitHub - SymbiFlow/symbiflow-docs: Documentation for SymbiFlow (at github.com)
<daniellimws> mithro: Do you want me to make a pull request instead? This would be faster?
<tpb> Title: Primitive Block Timing Modeling Tutorial SymbiFlow (at symbiflow.readthedocs.io)
<daniellimws> Oh what happened
<mithro> @daniellimws Dunno what is going on there, log a bug and Robert Winkler will track it down
<daniellimws> Alright
<_whitenotifier-3> [symbiflow-docs] daniellimws opened issue #244: VPR documentation does not show up in material theme - https://git.io/JfeXF
<daniellimws> mithro: Shall I also add the license headers while I'm adding to the documentation?
<mithro> @daniellimws Probably best to do that in a separate pull request?
<mithro> @acomodi: You probably want to reload the document you are editing
<daniellimws> mithro: Oh yes definitely
<sf-slack> <acomodi> @mithro Yep, thanks ;)
<mithro> rw1nkler: You should have an invite to the SymbiFlow organization now
<sf-slack> <rwinkler> @mithro, yes I have! Thanks
<mithro> rwinkler: i can assign you bugs if you accept :-P
<sf-slack> <timo.callahan> @mithro yes that was the issue -- foss-fpga-tools is the actual project. I was able to create the disk now.
<daniellimws> mithro: Should I also add the license headers to the verilog .sim.v sources in the v2x repo?
<sf-slack> <rwinkler> Oh, so it's too late... I've already accepted ;P
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<mithro> @daniellimws Fast work :-P
<daniellimws> :D
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<daniellimws> mithro: It seems that some modules in the tests do not have golden.pb_type.xml (such as https://github.com/SymbiFlow/python-symbiflow-v2x/tree/master/tests/clocks/dff_comb_one_clock) Are they left out because they are trivial enough?
<tpb> Title: python-symbiflow-v2x/tests/clocks/dff_comb_one_clock at master · SymbiFlow/python-symbiflow-v2x · GitHub (at github.com)
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<mithro> daniellimws: Maybe they haven't been finished? :-P
<daniellimws> mithro: Haha then shall I add them as I update the docs?
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<mithro> daniellimws: Log issues first
<mithro> daniellimws: mkurc and kgugala might be able to give more info too
<mithro> daniellimws: git blame might be useful
<daniellimws> Ok sure thing
<_whitenotifier-3> [python-symbiflow-v2x] daniellimws opened issue #40: Missing golden.pb_type.xml in some test cases - https://git.io/JfeQL
<mithro> FFY00: FYI - I'm trying to document the status of the "SymbiFlow Flows" in this doc currently -> https://docs.google.com/document/d/1Q8vaqD67aqPO7JbSDZtVvbg4BD7XBVuA_JJTwcYHprk/edit#heading=h.3wym5vue0am1
<tpb> Title: SymbiFlow Flows Status - Google Docs (at docs.google.com)
<FFY00> okay
<tpb> Title: SymbiFlow process for managing branches on non-SymbiFlow owned projects (and how to merge) - Google Docs (at docs.google.com)
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<tpb> Title: Data Flow in SymbiFlow Arch Defs for Xilinx Series 7 Testing + Verification - Google Drawings (at docs.google.com)
<tpb> Title: SymbiFlow Checking / Testing Approach - Google Docs (at docs.google.com)
<tpb> Title: Types of "testing" in LiteX (and Migen/MiSoC) - Google Docs (at docs.google.com)
<tpb> Title: SymbiFlow Bitstream Verification Process - Google Drawings (at docs.google.com)
<mithro> FFY00: I figured out how to test multiple Linux on Travis with https://github.com/google/verible/blob/master/.travis.yml
<tpb> Title: verible/.travis.yml at master · google/verible · GitHub (at github.com)
<tpb> Title: Pull Requests · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro> daniellimws: You missed some files for the SPDX (mostly python)
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<mithro> FFY00: We build horrible static binaries for Verible and then test them on multiple OSs using the travis configation here -> https://github.com/google/verible/blob/master/.travis.yml
<tpb> Title: verible/.travis.yml at master · google/verible · GitHub (at github.com)
<FFY00> okay
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<tpb> Title: Open Source (FOSS) FPGA (EDA) Tooling Interchange Formats + Toolchain parts - Google Docs (at docs.google.com)
<FFY00> no
<FFY00> mithro, what do you think of using circleci? since it has native support for docker
<mithro> FFY00: That was an attempt to document the "flow ecosystem"
<FFY00> travis is a pain since have to make a script and then run it inside docker
<mithro> FFY00: I have a bigger one for ASIC tooling -- https://docs.google.com/document/d/1p-EJaC5kKgRahqcAxvEcEOVaIsi_ZObbBnwHjdaqSjc/edit#heading=h.qq7cizdf7hl2
<tpb> Title: Open ASIC EDA Tooling Random Diagrams - Google Docs (at docs.google.com)
<FFY00> maybe it's worth to put all this files in a shared google drive folder
<tpb> Title: SymbiFlow - Publically Accessible Docs – Google Drive (at drive.google.com)
<FFY00> yes
<FFY00> didn't have that link :)
<mithro> FFY00: Are somewhat trying to wean myself off the GDocs habbit
<FFY00> yeah
<mithro> 100% unsuccessfully however :-)
<FFY00> they are super useful
<FFY00> mithro, would it be fine to user circleci instead of travis
<FFY00> don't know if you missed my message above
<mithro> Travis is the preferred tool
<mithro> Consistency is good :-)
<FFY00> yes, but travis is missing native docker support
<FFY00> which makes things a bit clunky
<FFY00> since I will have to maintain a script outside .travis.yml to do things
<mithro> FFY00: It's pretty common to have .travis.yml set up some stuff and then call a script a normal user would call (In fact that is probably the preferred way)
<FFY00> see the circle example here: https://circleci.com/docs/2.0/circleci-images/
<tpb> Title: Pre-Built CircleCI Docker Images - CircleCI (at circleci.com)
<tpb> Title: Using Docker in Builds - Travis CI (at docs.travis-ci.com)
<mithro> FFY00: I would say that Google Cloud Build would be the best option if you are thinking about something with more "docker native" support -- as we have a large amount of free resources there
<FFY00> that works for me
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<FFY00> are you fine using it or do want travis?
<mithro> I prefer travis, but would take cloud build
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