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[vtr-verilog-to-routing] tpagarani opened issue #537: Analysis option in VTR does not generate Blackbox timing in SDF correctly - https://git.io/JJqLr
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[symbiflow-arch-defs] acomodi opened issue #1580: SRL tests fail if top outputs are connected to GND with new Yosys - https://git.io/JJqBj
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[prjxray] andrewb1999 opened issue #1388: SDF generation produces lowercase CELLTYPE for routing_bel in slicel/slicem - https://git.io/JJqay
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