<daveshah>
Yeah, I remember it being mentioned on #yosys a little while ago
<daveshah>
I told them to post it here at the time but I can't remember if they did
<litghost>
andrewb1999: > With 500 kbps baudrate I get a bunch of lines starting with L and then random characters
<litghost>
That is what we expect
<litghost>
andrewb1999: xc/xc7/tests/common/read_uart.py is the tool for reading that data
<litghost>
andrewb1999: There is one thing to be aware of. read_uart.py hard codes the address and data widths
<litghost>
andrewb1999: You do need make sure they are in sync
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<litghost>
andrewb1999: I checked, and I believe read_uart is setup for 16-bit address and 16-bit data widths, which is the default of what bram_test is doing
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<litghost>
andrewb1999: Can you make a PR with the RAMB36 changes? I think I just ran into an issue that might be directly relevant
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<sf-slack>
<arildj78> I'm just getting started with FPGA and how ordered an Icebreaker dev board. As soon as I've moved past a Blinky, I would like to create a pretty narrow bandpass filter with steep falloff. Are there any packages I should be looking at to help me create a bitstream to load onto the fabric?
<sf-slack>
<arildj78> I'm looking for a 455kHz filter, I'm not sure if I'm able to pull it off on the icebreaker though.
<litghost>
arildj78: What sample rate do you believe you need for your filter? Also are you trying to do ADC -> DAC or a pure digital path?
<sf-slack>
<arildj78> My signal is the intermediate frequency from a radio receiver, so I would have to throw in an ADC in the mix as well. As for sampling, I'm thinking 10MSamples/sec but I'm open for suggestions.
<litghost>
arildj78: How wide of an ADC do you believe you need?
<sf-slack>
<arildj78> The output should end up as an Received Signal Strength Indicator, so I'f I'm able to analyze the signal strength of my 455kHz in the FPGA, that would be awesome, if not I already have a chip that can to that job, but then I would have to send it to a DAC first.
<sf-slack>
<arildj78> Wide?
<litghost>
aruldj78: How many bits
<sf-slack>
<arildj78> As in bandwidth?
<sf-slack>
<arildj78> ahhh...
<sf-slack>
<arildj78> 12?
<sf-slack>
<arildj78> 16?
<litghost>
aruldj78: An RSSI indicator is probably easier done in hardware. Why do you believe you need such a narrow bandpass?
<sf-slack>
<arildj78> I'm trying to detect a faint signal in a lot of noise.
<litghost>
aruldj78: In that case you probably don't care about RSSI, but you really want an SNR. What kind of coding are you using?
<sf-slack>
<arildj78> The easiest solution would be a ceramic filter, but they are not as easy to source as they used to be.
<sf-slack>
<arildj78> Coding?
<litghost>
aruldj78: The reason I don't believe you want an RSSI is if you input signal is near the noise floor, I'm not sure how useful RSSI will be
<sf-slack>
<arildj78> For the FPGA, the micro, or something else?
<litghost>
aruldj78: If the input signal is near the noise floor, presumably you have some kind of encoding schema (reed-solomon, convolution) for error recovery
<sf-slack>
<arildj78> The signal will for sure start off below the noisefloor and then rise through it as I move closer to the source. I'm trying to maximize the distance where I'm able to detect the signal.
<sf-slack>
<arildj78> The signal is continous wave 455kHz.
<sf-slack>
<arildj78> The transmitter is on for approximately 100milliseconds and off for 900ms
<litghost>
arildj78: Do you have to deal with doplar shifts?
<sf-slack>
<arildj78> Those timings can very and is out of my control.
<sf-slack>
<arildj78> no dopplershift, but the frequency is defined as f_0 +-80Hz
<litghost>
arjildj78: 10 MS seems like overkill, I'd expect a 2 MS part could do the job. As for whether you could do a high order filter and meet timing in an icebreaker, I imagine you could prototype a low order filter and see how the final design resource count looks. If a 2nd order filter doesn't fit or doesn't meet timing, it's hard to believe you do a high order filter. I still think the easiest solution is a simple
<litghost>
bandpass filter in hardware, and then a low rate ADC could easily read the RSSI
<litghost>
arjildj78: Actually even 2 MS is still probably overkill, as most of the energy should be narrowly at 1 frequency in your +/- 80 Hz. How clean is the CW source? If the source doesn't have extra harmonic, do you really need a super high sampling rate?
<sf-slack>
<arildj78> I haven't scrapped that idea of an discrete BP in hardware, but this is also a learning possibility for me.
<sf-slack>
<arildj78> If I were to try this with the FPGA, what kind of tools should I look for the help me set up the filter.
<litghost>
arildj78: A second order discrete bandpass is really easy to code. It won't get you super high cutoff, but I'm not really convinced that is needed in this case
<sf-slack>
<arildj78> I would think that someone has designed something like this before, so I wouldn't have to learn everything down to each calculation. Maybe there are code to be cloned or a tool to enter parameters for my filter in.
<sf-slack>
<arildj78> Can you point me in the direction of a tutorial, a repo, or even an appropriate book?
<sf-slack>
<arildj78> Leaving keyboard for 10 minutes.... will be back
<litghost>
arildj78: Any discrete filtering class would cover low order bandpass filters immediately after discussing low pass and high pass filters
<litghost>
Once you have the FIR coefficients, the FPGA implementation isn't too hard. The order of the filter will determine how many memory elements you need and multipliers
<sf-slack>
<arildj78> Do you think I should start off with the icebreaker and symbiflow, or are there any other packages I should go for at the beginning?
<litghost>
arildj78: In the case of icebreaker, you definitely want yosys + nextpnr
<sf-slack>
<arildj78> Both part of the symbiflow project?