00:02 <daniellimws> mithro: Wanna take some time to do the migration? https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams/pull/49

00:02 <tpb> Title: Support nMigen and RTLIL inputs by daniellimws · Pull Request #49 · SymbiFlow/sphinxcontrib-verilog-diagrams · GitHub (at github.com)

00:02 <daniellimws> We'd have to rename the repo and create the compat version at the same time to not break anything

00:46 <mithro> litghost / andrewb1999: Does this look fine -- https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master ?

00:46 <tpb> Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)

00:46 <litghost> mithro: mkurc should review

00:47 <litghost> But looks okay from my perspective

01:33 <_whitenotifier-b> [prjxray] andrewb1999 opened issue #1402: Zybo and basys harnesses do not contain explicit type - https://git.io/JJlMI

02:09 <mithro> daniellimws: Yes we should figure out when to do that

02:09 <mithro> I'm still kind of snowed under with the skywater-pdk related stuff

02:10 <sf-slack> <benglines1> @kgugala I've submitted a pull request for a bug that I found with https://github.com/SymbiFlow/symbiflow-bitstream-viewer that will correctly output all the bit locations for features with multiple bits. I don't see any other issues with the functionality, but perhaps there is something else that you know about? There also seems to be 3 major functionalities from bithtml.py: run, run_vue, and run_dump_grid. The

02:10 <sf-slack> titles of these functions aren't very descriptive so it took some time for me to figure out what was going on It seems like run_vue creates a .json file with the bits organized by frame, but as far as I can tell, nothing is done with that .json file. Do you know anything about what was the intention for the run_vue function? Is there something that I'm not understanding?

02:10 <tpb> Title: GitHub - SymbiFlow/symbiflow-bitstream-viewer: Tool for graphically viewing FPGA bitstream files and their connection to FASM features. (at github.com)

02:16 <mithro> mkurc: Can you check that pull request, if it looks okay I'll push it tomorrow morning

02:29 <daniellimws> mithro: Ok can just let me know whenever you wanna do it

02:30 <daniellimws> mithro: What's the status of skywater-pdk now?

04:46 <sf-slack> <benglines1> Anybody used the bit2fasm tool yet with prjuray? I just tried to use it on a bitstream that I expected to only output 100ish lines of fasm but it seemed to output every fasm possible (around 600,000) This happening for anyone else?

04:46 <sf-slack> <benglines1> *700,000

07:16 <sf-slack> <mkurc> @mithro: Sure, I'll check the prjxray db PR

07:55 <daveshah> benglines1: UltraScale+ devices have all unused LUTs set to output 1 by default, to save power

07:55 <daveshah> this results in loads of extra set bits in the FASM

07:56 <daveshah> it might be nice to have a bit2fasm option that skips these

09:43 <sf-slack> <kgugala> @benglines1 the PR is now marged, thanks for the fix

09:44 <sf-slack> <kgugala> @benglines1 the vue run was an initial idea to get the bit info, but it turned out to be slow and consume a lot of RAM so we added the `--dump_grid` switch and use it in the flow

11:51 <_whitenotifier-b> [sv-tests] MikePopoloski opened issue #955: slang build is a couple months old - https://git.io/JJ8tj

11:54 <sf-slack> <mkurc> @mithro @litghost Regarding the latest prjxray db change: I confirm that IOI3 features are correct, not sure about mask files though. Can't tell anything about changes to DSP timings.

14:43 <_whitenotifier-b> [prjuray] litghost opened issue #24: Add option to bit2fasm to skip emitting empty CLE sites - https://git.io/JJ8n5

14:47 <litghost> mithro: I think the new prjxray-db can be pushed

15:37 <litghost> benglines1: Did you use "--suppress_zero_features"? I found a similiar problem when I first brough up bit2fasm, and added "--suppress_zero_features" to handle some of the noise

16:14 <sf-slack> <benglines1> @litghost that certainly helps to cut down on the size, thanks! From my understanding, the --suppress_zero_features mode just omits any fasm that is not associated with any specific bits, right? I am still seeing all of the unused LUTs in my design though after using "--suppress_zero_feature"

16:29 <_whitenotifier-b> [make-env] mithro opened issue #15: Support providing the environment using docker rather than conda - https://git.io/JJ845

16:30 <_whitenotifier-b> [make-env] mithro opened issue #16: Support providing the environment using virtualenv and system binaries - https://git.io/JJ84j

16:32 <_whitenotifier-b> [make-env] mithro opened issue #17: Support providing the environment using nix - https://git.io/JJ8Bk

19:01 <tnt> kgugala: Do you know the status of the true LUT4 support (instead of 2*lut3 + fmux) support and of the direct LUT->FF path in the quick logic support ?

20:20 <_whitenotifier-b> [FPGA-Tool-Performance-Visualization-Library] HackerFoo opened issue #7: Compare a given list of evaluations - https://git.io/JJ8V4

20:23 <_whitenotifier-b> [FPGA-Tool-Performance-Visualization-Library] HackerFoo opened issue #8: Computed Columns - https://git.io/JJ8Vz

20:26 <_whitenotifier-b> [FPGA-Tool-Performance-Visualization-Library] HackerFoo opened issue #9: Filtering and aggregating projects - https://git.io/JJ8VK

20:28 <_whitenotifier-b> [FPGA-Tool-Performance-Visualization-Library] HackerFoo opened issue #10: Dashboard Python Notebook - https://git.io/JJ8VM