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<sf-slack> <timo.callahan> @kgugala -- regarding https://github.com/antmicro-labs/tensorflow/tree/speech_zephyr/tensorflow/lite/micro/examples/micro_speech/zephyr_riscv -- do I need to add a special LiteX peripheral for the I2S? Or not if it's just bitbanging? Does the I2S PMod need to be on a particular slot on the Arty board? Should I try to adapt what you have for I2C here --
<tpb> Title: tensorflow/tensorflow/lite/micro/examples/micro_speech/zephyr_riscv at speech_zephyr · antmicro-labs/tensorflow · GitHub (at github.com)
<tpb> Title: litex-buildenv/tf.py at master · timvideos/litex-buildenv · GitHub (at github.com)
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<sf-slack> <kgugala> @timo.callahan the demo requires this IP https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/i2s.py
<tpb> Title: litex/i2s.py at master · enjoy-digital/litex · GitHub (at github.com)
<sf-slack> <kgugala> and we were testing it with https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
<tpb> Title: Pmod I2S2: Stereo Audio Input and Output - Digilent (at store.digilentinc.com)
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<sf-slack> <timo.callahan> @kgugala thanks for the link!
<sf-slack> <timo.callahan> @kgugala I've got the PMod already, excited to use it ...
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<andrewb1999> Does anyone in here know about constant nets in 7 series? I'm trying to define an ROI that covers multiple clock regions and I'm running into issues with being unable to route constant nets across the clock region boundary.
<andrewb1999> I can provide more information is anyone is able to help
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