<sf-slack>
<cwl11> @litghost Yes, but say for example when only inputs A2 and A1 are the only wired inputs. When trying to manually change the lookup table in my bitstream, A2,A1 = LUT[63], A2,!A1=LUT[62], !A2,A1=LUT[61], !A2,!A1=LUT[60]. Its like the highest possible input for the LUT gets shifted to the MSB of the LUT
kraiskil has quit [Ping timeout: 246 seconds]
tannewt_ has joined #symbiflow
pdp7_ has joined #symbiflow
hzeller_ has joined #symbiflow
hzeller has quit [*.net *.split]
pdp7 has quit [*.net *.split]
tannewt has quit [*.net *.split]
_whitenotifier-b has quit [*.net *.split]
tannewt_ is now known as tannewt
pdp7_ is now known as pdp7
promach3 has quit [Write error: Connection reset by peer]
nurelin has quit [Remote host closed the connection]
xobs has quit [Write error: Connection reset by peer]
lopsided98 has quit [Ping timeout: 244 seconds]
lopsided98 has joined #symbiflow
xobs has joined #symbiflow
nurelin has joined #symbiflow
promach3 has joined #symbiflow
lopsided98 has quit [Ping timeout: 260 seconds]
lopsided98 has joined #symbiflow
az0re has quit [Ping timeout: 240 seconds]
maartenBE has quit [Ping timeout: 256 seconds]
az0re has joined #symbiflow
maartenBE has joined #symbiflow
kraiskil has joined #symbiflow
hzeller_ has quit [Read error: Connection reset by peer]
hzeller_ has joined #symbiflow
tcal has joined #symbiflow
kraiskil has quit [Ping timeout: 256 seconds]
craigo has quit [Ping timeout: 256 seconds]
<litghost>
cwl11: So you are not thinking about how the hardware functions quiet right. The 7-series LUT is always a LUT6_2, no matter the width of the equation being implemented
<litghost>
cwl11: LUT.INIT[{A5,A4,A3,A2,A1}] = O5 and LUT.INIT[{A6,A5,A4,A3,A2,A1}] = O6 is always true
<litghost>
cwl11: When mapping smaller LUT equations onto the O6 or O5 outputs, the P&R tool needs to choose how to relate the library cell pins (e.g. I0, I1 ... I5) onto the physical BEL pins (e.g. A1, A2 ... A6)
<litghost>
cwl11: It turns out that the higher pins (e.g A6 is higher than A5) have less combinatoral delay than the lower pins (A1)
<litghost>
cwl11: So a LUT2 will typically be implement using the A5 and A6 pins
<litghost>
cwl11: However the equation LUT.INIT[{A6,A5,A4,A3,A2,A1}] = O6 is still true, and depending on what signal is routed to A4 .. A1, then the equation has to change
<litghost>
cwl11: By default A1 .. A6 route to the local VCC / HARD1 site pin, e.g. a logic '1'
<litghost>
cwl11: So the relevant bits are LUT.INIT[{A6,A5,'1',1',1','1'}] = O6
<litghost>
cwl11: But it is worth noting that because the 7-series CLB's support fracturing, then the equation can be more complicated if both the O6 and O5 outputs are in use, because rather than have the other pins as '1', then are "don't-care", e.g. the init bits are set such that the equations hold regardless if the unused pins are '0' or '1'
robert2 has joined #symbiflow
<sf-slack>
<cwl11> @litghost Okay thank you that makes sense. So does vivado not tell me the correct inputs? When I look at the LUT6_2 in my design being used, it shows sw0 going to A3 and btn0 going to A2, and they are ORed together. But when I modify the LUT values, its as if they are going to A6 and A5. Should I just assume that smaller LUT will get shifted to have its inputs in A6 depsite what vivado shows?
<litghost>
cwl11: Vivado has LOCK_PINS to control the behavior here
<litghost>
cwl11: The thing to pay attention here is the relationship between the cell pin -> bel pin
robert2 has quit [Quit: WeeChat 1.9.1]
_whitenotifier-3 has joined #symbiflow
<_whitenotifier-3>
[symbiflow-arch-defs] andrewb1999 opened issue #1636: Support multi clock region ROIs - https://git.io/JJ9zh
<sf-slack>
<cwl11> @litghost So I0 is going to A2 and I1 is going to A3. But if there is no constraint on LOCK_PINS, they go to A6 and A5?
<litghost>
cwl11: If LOCK_PINS is not set, the Vivado router is free to remap I0/I1 to any of the 6 pins
<sf-slack>
<cwl11> @litghost Okay, thank you! I understand now
<sf-slack>
<nelson> Would like to fire up and run fasm2bels on a simple design. Not sure what to provide for the --connection_database parameter nor how to build such a database. Suggestions welcomed. Will take what I learn and add installation verbiage to the README.md if that will help others. Thanks!
<litghost>
nelson: It's a path to where to keep the database