#symbiflow on 2020-08-21 — irc logs at freenode.irclog.whitequark.org

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02:56 <ske33> Thanks sf-slack .......... :)

03:04 <sorear> sf-slack is a bridge bot, the last user who spoke through it was timo.callahan

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03:09 <sf-slack> <timo.callahan> It's confusing :)

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10:22 <_whitenotifier-3> [symbiflow-arch-defs] rw1nkler opened issue #1645: Incorrect PLL-BUFG-BUFGMUX handling - https://git.io/JJjWk

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19:17 <jopdorp> sup y'allll

19:17 <jopdorp> :p

19:17 <jopdorp> I'm Jegor

19:18 <jopdorp> I'm a software engineer and a starting fpga enthousiast

19:18 <jopdorp> I've implemented a couple of projects in verilog using verilator, icarus and modelsim(the compiler from quartus)

19:19 <jopdorp> I really like using verilator and icarus because open source rocks!

19:19 <jopdorp> now the thing is that my fpga is a Cyclone V

19:19 <jopdorp> I have that because of the MisTer project

19:20 <jopdorp> Is anyone looking at Cyclone V support, and if not, how would I start on Cyclone V myself?

19:23 <jopdorp> i found the yosys and vtr-verilog-to-routing repos

19:24 <jopdorp> is there a core symbiflow repo?

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19:46 <Lofty> jopdorp: Hi, I'm working on reversing the Cyclone V along with Sarayan (who isn't in this channel)

19:46 <Lofty> Well, to be more precise, we've mostly reversed Quartus to obtain information on the Cyclone V

19:47 <Lofty> Work for it isn't really associated with Symbiflow, so we work in #prjmistral instead

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20:29 <jopdorp> Lofty: that's awesome I'm keen to have a look

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