#symbiflow on 2021-03-22 — irc logs at freenode.irclog.whitequark.org

04:00 <_whitenotifier-4> [fasm] the-centry opened issue #66: If there someone could tell me how to install fasm in windows? - https://git.io/JmbkN

13:15 <_whitenotifier-4> [fpga-tool-perf] olofk opened issue #320: Adjust to changes in Edalize icetime invocation - https://git.io/JmNPQ

15:57 <litghost> mithro: LGTM for db update

16:02 <mithro> litghost: Database updated then

16:02 <mithro> litghost: BTW I have some updates to your rapidyaml python packaging pull request

16:03 <litghost> Feel free to just push a new PR if you know how to fix the issues

16:03 <litghost> Just grab my branch from my fork, etc

16:03 <litghost> Or you could push a copy to a symbiflow-fork so we can both hack on it

16:19 <sf-slack> <nils.albartus>

16:19 <sf-slack> <nils.albartus> Hey guys, I have a bitstream generated from Vivado for the zedboard. I tried to use the fasm2bel tool to get a netlist out of it. for some reason it crashed, because (and thats my best bet) when trying to recreate the routes it finds a pip of type hint, which I guess does not make sense. any idea how to fix this?

16:21 <sf-slack> <nils.albartus> i would be fine if the tool might give me some not complete netlist with some connections missing. is this error coming up due to an incomplete database?

16:21 <litghost> Possible

16:21 <litghost> fasm2bels can only really work on bitstreams that are complete

16:22 <sf-slack> <nils.albartus> the bitstream is complete

16:22 <litghost> Incomplete nets do prevent it from working, and that isn't that suprising

16:22 <litghost> The bitstream database is completely, e.g. the bitstream is completely understood

16:22 <sf-slack> <nils.albartus> ah okay

16:22 <sf-slack> <nils.albartus> so what do you suggest?

16:22 <litghost> If you look at the output, are there any "unknown" bits?

16:23 <sf-slack> <nils.albartus> i sent you the entire output above

16:23 <litghost> We'll, first see if the output of "bit2fasm --verbose" reports any unknowns

16:23 <sf-slack> <nils.albartus> okay

16:29 <sf-slack> <nils.albartus> ```# In frame 0x0042001a 6 bits were not converted. { unknown_bit = "0042001a_16_7", unknown_segment = "0x00420000", unknown_segbit = "26_519" } { unknown_bit = "0042001a_17_25", unknown_segment = "0x00420000", unknown_segbit = "26_569" } { unknown_bit = "0042001a_28_7", unknown_segment = "0x00420000", unknown_segbit = "26_903" } { unknown_bit = "0042001a_29_25", unknown_segment = "0x00420000", unknown_segbit =

16:29 <sf-slack> "26_953" } { unknown_bit = "0042001a_97_7", unknown_segment = "0x00420000", unknown_segbit = "26_3111" } { unknown_bit = "0042001a_98_25", unknown_segment = "0x00420000", unknown_segbit = "26_3161" } # In frame 0x0042001b 2 bits were not converted. { unknown_bit = "0042001b_59_6", unknown_segment = "0x00420000", unknown_segbit = "27_1894" } { unknown_bit = "0042001b_60_24", unknown_segment = "0x00420000", unknown_segbit =

16:29 <sf-slack> "27_1944" } # In frame 0x00420025 2 bits were not converted. { unknown_bit = "00420025_50_28", unknown_segment = "0x00420000", unknown_segbit = "37_1628" } { unknown_bit = "00420025_50_29", unknown_segment = "0x00420000", unknown_segbit = "37_1629" }```

16:29 <sf-slack> <nils.albartus> this is what you mean i guess?

16:30 <sf-slack> <nils.albartus> so i probably need to turn on the fuzzers? anyway to specifically target them to my missing bits?

16:34 <litghost> Yes

16:34 <litghost> And yes

16:34 <litghost> First step is to do a gross check to see "where" in the tile grid those bits are

16:34 <litghost> E.g. which column / tile the bits likely are associated with

16:35 <litghost> We've recently documented more bits in the GTP, but those fuzzers only run on artix

16:35 <sf-slack> <nils.albartus> alright how do i that? can i create a FASM file?

16:35 <litghost> We've also documented some more DSP bits

16:35 <litghost> Be more specific?

16:35 <litghost> Your second question doesn't really make sense

16:36 <sf-slack> <nils.albartus> how to i do the “gross check”?

16:36 <litghost> Just grep the tilegrid.json for your device

16:55 <sf-slack> <nils.albartus> so maybe a few follow up questions: • the frame where my missing bits are i know from the bit2fasm tool. how can i find more information in my tilegrid.json (which is in xc7z020s) to actually figure out what is missing? what exactly am i looking for (or to rephrase the question: what am i supposed to “grep”)? from my understanding there are certain configuration for the pips missing in the database, is this

16:55 <sf-slack> correct? • once i figure out which exact pip bits might be missing, what do i have to do next? i guess use the fuzzers to identify the missing bits in the database?

16:57 <litghost> So first off, they might be pips, they might not be

16:57 <litghost> Don't assume

16:58 <litghost> The segment address is the frame address in tilegrid, and generally corrisponds to 1 column

16:58 <litghost> Tiles within a column are typically linearlly addressed

16:58 <litghost> So bits with low word offsets appear in tiles earlier than bits with high word offsets

16:59 <litghost> So between knowing which column of the grid the bits fell, and bounding the tile range based on the word offset, you can usually narrow down which tile the bits belong too

16:59 <litghost> From there, it is a matter of either fixing or writing a fuzzer to document the remaining bits

17:00 <litghost> Alternatively, if the bits belong to an optional feature (e.g. DSP or XADC), just remove those from your designs

17:02 <sf-slack> <nils.albartus> alright. i will give this a shot tomorrow. thanks for the first initial push ;)

17:10 <bryce_> Hello! I was wondering if there was a source of information where I could go to get a broad overview of the functional status of the project, and in particular the xilinx reverse engineering effort. Something like a "state of the project" blog, so I can keep tabs on it without lurking here or following a bunch of other sources? The open source FPGA efforts are of great interest to me, but unfortunately I'm balancing my research interests

17:10 <bryce_> with an early-stage medical career and I don't have as much time as I'd like to keep tabs on how this is going.

17:11 <bryce_> TLDR - is there a place I can go to keep track of the progress of project xray, symbiflow etc without following a bunch of twitters or IRC channels, so I can know when the time is right to drop the $$ for a Xilinx dev board?

17:13 <litghost> https://github.com/antmicro/symbiflow-examples is where we put our functional demos

17:13 <litghost> So for example, there is a linux capable SoC with DDR and ethernet up there

17:14 <litghost> That isn't precisely what you are asking for

17:14 <bryce_> It isn't, but that's pretty helpful; I have enough technical background to have a broad sense of how hard various things are, so it helps to know what people have got working.

17:14 <bryce_> So, thanks, that's useful at least.

17:17 <bryce_> I'm really looking forward to seeing where FPGAs go when they're free of these awful proprietary development tools

18:24 <bryce_> On an unrelated note, I went to buy a dev board and saw this weird thing on ebay, obviously not a dev board: https://www.ebay.com/itm/284146993530 <- What the heck needs TEN Virtex-6 FPGAs but has no visible RAM or high-speed interfaces? Very strange, really curious what it could be for.

18:24 <tpb> Title: Qty:10 On Board Xilinx Virtex-6 XC6VLX130T | eBay (at www.ebay.com)

22:53 <mithro> This looks super cool -> https://github.com/pypa/setuptools/issues/new/choose

22:54 <mithro> Looks like we need https://github.com/pypa/setuptools/blob/main/.github/ISSUE_TEMPLATE/config.yml ...

23:56 <mithro> litghost: Have you seen "ImportError: dynamic module does not define module export function (PyInit_ryml)"

23:57 <litghost> No

23:57 <litghost> I assume it is what it says on the tin?

23:57 <litghost> E.g. visibility rules only the SO mark it as not visible

23:57 <litghost> What happens if you run "nm" or equiv?