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<arvindsrinivasan> This looks great as an improvement, thank you Lofty
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<dan.ravensloft> It's not a fix, but yeah
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<pingkan.wewengkang> Hi Everyone! I'm Cindy. I'm an FPGA engineer, and I'm interested to contribute to the open source FPGA projects. I am comfortable with Verilog and Python, and I have some experience with TCL scripting. Please do let me know of any available opportunities!
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<dan.ravensloft> Welcome!
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