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<_whitenotifier-5> [python-fpga-interchange] acomodi opened issue #61: Invalid DCP when the BUFG route-thru is used - https://git.io/JOtZu
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<mithro> krzychuczternasty: No current support or planned support for Intel hardware at the moment. There is a project from Lofty around trying to fix that however.
<Lofty> We have Cyclone V bitstream info
<Lofty> Just not PnR
<sf-slack> <cjearls> What's the difference between having information about the bitstream and being able to place and route?
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<Lofty> cjearls: bitstream information is "given a bitstream, we can dump the netlist"; place and route is "given a netlist, we can produce a bitstream"
<Lofty> Which is a much harder task :P
<sf-slack> <cjearls> I see. So the documentation to start with is there, but support for the PnR tools is not?
<Lofty> Correct
<Lofty> I was trying to get nextpnr to target Cyclone V, but in general PnR requires climbing up a cliff to get an MVP#
<sf-slack> <cjearls> What could someone with a Cyclone V do to help the process?
<sf-slack> <dan.ravensloft> Switching to Slack because I just finished a meeting
<sf-slack> <dan.ravensloft> You don't even need a Cyclone V to help; I have a fork of nextpnr on my GitHub, and basically you have to implement all the nextpnr core API to get something
<sf-slack> <dan.ravensloft> For personal reasons I'm not presently considering VPR
<sf-slack> <dan.ravensloft> We have a library that exposes all the FPGA information - `libmistral`
<sf-slack> <dan.ravensloft> But there's a bit of impedance matching needed there.
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<sf-slack> <cjearls> So are you going to be adding your changes to upstream nextpnr, or making an Intel-specific tool for PnR?
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<sf-slack> <khanvms9> Is Edalize Project Supported on python 3.5?If yes Please checkout this PR
<sf-slack> <acomodi> V. M. Shahbaaz Khan: the symbiflow fork of Edalize still needs to be updated to track upstream, and the changes in there upstreamed. I believe that you may push the fix directly to upstream https://github.com/olofk/edalize (if the fix is still valid)
<sf-slack> <krzychuczternasty> So there's nothing started for cyclone 10 yet? What would be the first step in this direction? Should I try to reverse the cyclone 10 bitstream? Is there an option that it's similar to cyclone V? Note that i'm a bit of a noob in fpga
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<sf-slack> <dan.ravensloft> There is the Cyclone 10 LP and the Cyclone 10 GX
<sf-slack> <dan.ravensloft> These chips are completely different; the 10 GX comes from the Cyclone V, while the 10 LP is more like a Cyclone IV
<sf-slack> <dan.ravensloft> I'll be aiming to upstream them, yeah
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<sf-slack> <krzychuczternasty> I have cyclone 10 LP board and I'd like to have an open toolchain for that. What would you recommend me to start with?
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<sf-slack> <dan.ravensloft> I'll just use a thread for this. So, you would need to port Yosys first
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<kamyar> Hi everyone! I just saw the SymbiFlow ideas for GSoC and would be very interested to help with at least one of the proposals. Is it too late to start an application? I've never participated in GSoC and don't honestly know much about it, so greatly appreciate your feedback!
<mithro> kamyar: Depends on how much time you have to work on an application right now, if you have the time you can possible put something together before the deadline
<kamyar> mithro unfortunately kinda buried with work duties ATM, but started this proposal (based on the SymbiFlow idea):  https://docs.google.com/document/d/1-5ibWNSMXHXmTx7RLYyQ6hOQLy-QFZeusFjgX6YFxZ0/edit?usp=sharing
<tpb> Title: Google Docs: Kostenlos Dokumente online erstellen und bearbeiten (at docs.google.com)
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<kamyar> mithro Would greatly appreciate your thoughts on that idea!
<kamyar> I'm not actually quite sure how to move on towards finalizing the proposal, especially with only 20 hours left to the deadline :/
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<sf-slack> <mehaboob097> Hello Everyone Im an outreachy applicant and id like to work on the cross converter tool
<sf-slack> <mehaboob097> can anyone guide ke
<sf-slack> <mehaboob097> me
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