adjtm has quit [Remote host closed the connection]
infinite_recursi has joined #symbiflow
bjorkintosh has quit [Remote host closed the connection]
bjorkintosh has joined #symbiflow
<CarlosEDP>
Hi all, I'm building a Docker container with Symbiflow focusing portability... while it builds the Arty demo fine, it couldn't find an instance of PLL2_BASE IP I use on my design.
<CarlosEDP>
It was generated on Vivado Clocking Wizard...
<sf-slack>
<kgugala> hi CarlosEDP
<CarlosEDP>
Hey Karol! :)
<sf-slack>
<kgugala> I think PPL2_ADV isi supported
<CarlosEDP>
ah ok.. let me check and swap them
<CarlosEDP>
another question, the toolchain didnt support my constraints in the format of -dict...
<sf-slack>
<kgugala> maybe you need to set PYTHON_PATH?
<CarlosEDP>
humm.. maybe..
<sf-slack>
<mkurc> `conda env create` doesn't do that on its own. In symbiflow you run `make env` which creates the env and install pip packages.
<CarlosEDP>
ah ok... well, I added the pip install step in my Dockerfile
<mithro>
CarlosEDP: morning!
<CarlosEDP>
Hi Tim! Morning
<CarlosEDP>
I'm already poking some stuff... and bugging the folks around here :)
<mithro>
CarlosEDP: As I mentioned, there is still a lot of work to polish the Xilinx flow
curtosis has joined #symbiflow
Raito_Bezarius has quit [Ping timeout: 260 seconds]
<_whitenotifier-5>
[actions] acomodi opened issue #17: Third party dir not excluded by license check - https://git.io/JOcC1
Raito_Bezarius has joined #symbiflow
<mithro>
CarlosEDP: In *theory*, you should be able to just build Yosys+yosys_symbiflow_plugins+VPR+prjxray-tools and then use the datafiles compiled from symbiflow-arch-defs rather than using conda directly.
vup has quit [Ping timeout: 245 seconds]
vup has joined #symbiflow
<CarlosEDP>
Yep! Right now I'm doing the default install but my idea is that..
<CarlosEDP>
since the container doesn't need examples and etc
<CarlosEDP>
Just updated the Dockerfile, works fine now. I was able to build my test project and program it to the Arty with Vivado.
<sf-slack>
<kgugala> CarlosEDP: you can also program those boardswith openOCD
<sf-slack>
<kgugala> CarlosEDP - it's not really an error (however it looks like so)
<CarlosEDP>
kgugala:
<CarlosEDP>
great... gonna try with it too
<sf-slack>
<kgugala> it's more like info message saying that bitstream writer will not use antlr (faster implementation) and it's falling bach to slower (pure python based)
<CarlosEDP>
yep.. thought it "should" work with the default antlr... and it didn't for some error
<CarlosEDP>
Full opensource without VMs, Windows, Vivado...
<sf-slack>
<kgugala> YaaaY!!
<sf-slack>
<kgugala> now - time to open source the chip itself ;)
<CarlosEDP>
now, run it on FuseSoc ;)
<CarlosEDP>
with containers
<CarlosEDP>
except openocd part since on Mac/Windows you can't do USB passthru from plugged devices to the container... we were discussing this on Twitter other day
gsmecher has joined #symbiflow
ASHR has joined #symbiflow
<CarlosEDP>
there is only one "issue" with Symbiflow on a container... the size
<sf-slack>
<acomodi> If you are interested in only the arty, the xc7a50t is enough
<sf-slack>
<acomodi> (unless is the 100T arty version)
<mithro>
CarlosEDP: How good is your C++? Those files compress *really* well, it would be awesome to see if there was much of a performance impact from reading a compressed version.
<mithro>
CarlosEDP: But so far it has generally been cheaper for me to send people hard drives then spend the developer time on that :-)
<_whitenotifier-5>
[sphinx_symbiflow_theme] mithro opened issue #7: Migrate all the projects to the new sphinx theme - https://git.io/JOczm
<mithro>
nextpnr uses flattened databases for ice40 and a more compressed format for the ecp5
<sf-slack>
<cjearls> Several months ago, I received a recommendation to buy an OrangeCrab FPGA as a starter FPGA. I've really enjoyed trying it out, and I'm back looking for another recommendation. I have several hundred dollars to spend, and I'd like to purchase a larger FPGA, the OrangeCrab can only fit one Vexriscv core, and I'd like to be able to fit multiple. If possible, I'd like a board that works with the linux-on-litex project and
<sf-slack>
has an FPGA-accessible ethernet port and FPGA-accessible microSD card slot or SATA port. I'd like the board to have plenty of RAM for Linux. Also, I think I'm interested in working with HDMI or DisplayPort inputs and/or outputs in the future, so built-in FPGA-accessible ports for this and would be nice, or if not, PMODs or some other connector that can be adapted to display standards. Is there something like that with SymbiFlow
<sf-slack>
support?
<sf-slack>
<cjearls> Also, the more example files that are available for a board, whether open-source or through the manufacturer, the better
<mithro>
cjearls: The Arty A7-100T or the higher end Nexys Video boards are nice (non-open source boards) but the open source Xilinx tooling is a bit rougher
<mithro>
cjearls: Higher end ECP5 boards are still less common, Greg Davill's ButterStick is kind of interesting
<CarlosEDP>
ULX3S from Radiona is nice, there's a 85k LUT version and uses the full open-source toolchain
<CarlosEDP>
like your OrangeCrab
<mithro>
cjearls: What ECP5 variant of the OrangeCrab do you have?
<CarlosEDP>
But honestly as a beginner I found the Digilent boards amazing, in both quality and documentation
<mithro>
The Digilent boards are heavily used in education, it is one of the reason Xilinx is the dominate FPGA company because everyone learns with their boards....
<tpb>
Title: FPGA Bitstream for Xilinx Artix7 running on FuseSoc containers with open source toolchain - asciinema (at asciinema.org)
ASHR has joined #symbiflow
<sf-slack>
<cjearls> I have the 25k LUT Orangecrab
<zyp>
did somebody suggest the ecpix-5 yet?
<sf-slack>
<cjearls> And I actually have a Genesys2 Kintex-7 on me currently, but I'm pretty sure the professor I'm working with is going to want it back once I graduate this semester :(
<zyp>
the ecpix-5 got both ethernet, microsd, sata, 512MB RAM, hdmi out, and 8 pmod sockets, so it seems like a good fit for your requirements
<sf-slack>
<cjearls> It looks like the ecpix-5 only has 256MB of RAM, otherwise, it's pretty tempting
<sf-slack>
<cjearls> Also the 85k LUT model is out of stock :S
curtosis is now known as curtosis[away]
curtosis[away] has quit [Quit: My Mac Mini has gone to sleep. ZZZzzz…]
rj has joined #symbiflow
<mithro>
Oh yeah - the lambdaconcepts boards are pretty good!
<mithro>
cjearls: I might be tempted to send a Genesys2 Kintex-7 to a person who got it working well in SymbiFlow.... I've sent 2 people that board for other reasons before.....
<mithro>
CarlosEDP: will attest to the fact that doing cool things get you cool hardware :-)
<CarlosEDP>
yes it does!
<sf-slack>
<cjearls> What remains to be done to have it working well in SymbiFlow? It's something I'm absolutely interested in helping with
<CarlosEDP>
<mithro "cjearls: I might be tempted to s"> can I get in line? 😃
<sf-slack>
<cjearls> As a heads-up, my thesis is due at the beginning of next month, after which I'll be moving across the country, so for the next couple weeks, I'm pretty slammed. Once I move, I'll have just under a month before I start my job that I'd love to spend helping improve Genesys2 Symbiflow support
<mithro>
The work to add support can be almost entirely done without needing the hardware
<sf-slack>
<cjearls> Oh, awesome
<sf-slack>
<cjearls> And to be fair, until I move, I have a Genesys2 on loan from my university
<tpb>
Title: SymbiFlow Bitstream Verification Process - Google Zeichnungen (at docs.google.com)
<sf-slack>
<cjearls> I see. I have used Vivado briefly before, that seems like something I could do. Do the DRC and timing violation checks need to be implemented, or are there still bugs to work out, or something else?
<mithro>
cjearls: I think we don't know
<mithro>
cjearls: Also I think the biggest problem will be things like running out of memory and disk space and hence requiring other fixes before being able to move forward
<sf-slack>
<cjearls> Oh, ok, so that whole part of the bitstream verification is still to-do
<mithro>
Syed: It would be awesome to have https://github.com/google/verible in Visual Studio Code for linting and auto-formating your SystemVerilog code
<sf-slack>
<cjearls> So would the best way to start be to just choose an example project, and push it through Vivado and SymbiFlow, and compare the bitstreams?
<tpb>
Title: A sample EDA design verification workflow on Google Cloud | Google Cloud Blog (at cloud.google.com)
<mithro>
Syed: It is an example of using SLURM to improve an EDA simulation workload
<mithro>
The ‘tile1_mini’ regression has 46 tests. Running all 46 tile1_mini tests sequentially took an average of 120 minutes. The parallel run for tile1_mini with 10 auto-scaled SLURM nodes completed in 21 minutes—a 6X improvement!
<sf-slack>
<pgielda> @olof.kindgren too many channels ;)
<sf-slack>
<olof.kindgren> @pgielda Yeah. Although it's mostly just slighly different subsets of people in all of them :)
<sf-slack>
<pgielda> this makes it even harder
<sf-slack>
<pgielda> if it was a completely different set then it would be easier to track ;)
<mithro>
umarcor / Syed / CarlosEDP / olofk: Any idea what hammer / chipyard from Berkeley uses for this type of stuff?
<sf-slack>
<cjearls> Chipyard is AWS-based
gsmecher has quit [Ping timeout: 240 seconds]
<CarlosEDP>
Sorry, was in a quick "solder PCB break" ... hehe.. yesterday I almost ripped out the micro usb connector from a PCB I was testing... just soldered it.. the flux arrived 😃
<CarlosEDP>
Hi Syed! It's a pleasure
<CarlosEDP>
So Olof is around too... I'm on Matrix.. I don't see him
rj has quit [Ping timeout: 240 seconds]
<umarcor>
cjearls: since you asked last time, we added a list of boards to https://hdl.github.io/awesome/ Apart from the Arty, Nexys and others from Xilinx, you might like the ULX3S or the ECPIX-5. Both have variants with the ECP5 85F, which is larger than the one in the OrangeCrab (25F).
<tpb>
Title: Awesome HDL | Home (at hdl.github.io)
rj has joined #symbiflow
<umarcor>
Given the requirements you mentioned, I would recoment PYNQ or other Zynq based boards from Xilinx/Digilent. They provide 1-2 ARM cores running at 500-900MHz, plus the programmable region (FPGA) in the same SoC. However, your are yet dependent on vendor tools if you want to use them.
<umarcor>
mithro: Digilent boards are not only used but also discounted in education. I got my PYNQ at $65. Not through my uni, but just using my uni e-mail on the Digilent site.
<umarcor>
oh, now I see that ECPIX was mentioned later...
<umarcor>
suzizecat in gitter channel GHDL has a mixed-language synthesis example (VHDL, Verilog and System Verilog) and he is interested in havin mixed-language LSP support by combining Verible with GHDL and/or rust_hdl
<sf-slack>
<syed.ahmed.emails> thanks!
<sf-slack>
<syed.ahmed.emails> Tim and I were chatting that VSCode should become the default GUI for open source fpga toolchain :)
<yeti>
emacs!
<yeti>
:-P
<sf-slack>
<syed.ahmed.emails> hahah
<umarcor>
wrt being in this channel, I'm mostly always online, but I don't start the IRC client automatically. So, sometimes I might not see something. Ping me in gitter if you want to be sure.
<sf-slack>
<syed.ahmed.emails> I was hoping to annoy somebody with that
<umarcor>
syed, have a look at TerosHDL, the project from that last link
<umarcor>
however, we know of people which use GHDL's LSP with VSCode, vim or emacs. Hence, any "multilanguage" LSP might work regardless of the editor.
<umarcor>
mithro: I'm not aware of hammer/chipyard...
<umarcor>
jokes aside, the remote containers or remote wsl features of VSCode are really nice; but not open source.
<sf-slack>
<syed.ahmed.emails> nice! TerosHDL looks nice, although got a little confused with the name if it were a new HDL
<tpb>
Title: Teros Technology Develop hardware, take advantage of software tools (at www.terostech.com)
<umarcor>
despite the name, it's not a company AFAIAA, just a group of friends/colleagues
rj has quit [Ping timeout: 240 seconds]
<sf-slack>
<romckend> Hello, I work at BYU and we are using the python-fpga-interchange project as part of our bootcamp. We noticed that the DeviceResources python interface does not expose all of the constructs available in the capnp file generated by Rapid wright, and we are considering expanding it. Is there any specific reason why the python object structures do not have everything in the capnp file?