00:28 <_whitenotifier-5> [sv-tests] MikePopoloski opened issue #1463: Taiga core is completely busted - https://git.io/JOu7K

00:40 <cjearls> I have a Nexys A7 with the XC7A100T-1CSG324C being delivered on Tuesday, is there any way set up to test the fully open-source toolchain easily? I successfully built some of the examples in the symbiflow-arch-defs with VPR, but I'm not very experienced with CMake or Makefiles, so I'm not sure what commands I'd need to take out of that to run on my own projects

01:24 <_whitenotifier-5> [symbiflow-xc-fasm2bels] the-centry opened issue #59: Running bug? - https://git.io/JOuND

02:14 <mithro> cjearls: You want to use symbiflow-examples for how to use the tools in your projects.

14:13 <mithro> gatecat: As we have lost litghost and I'mn juggling a lot of things, you'll need to poke me aggressively if you need review on something with the fpga-interchange-schema stuff otherwise it'll probably get missed. The squeaky wheel gets the grease.

14:15 <gatecat> mithro: sure, I've just re-requested review on the default values one, nothing else is critical atm

14:16 <mithro> Normally I try and get something done within 24 hours, you have permission to poke me at least once every 24h for anything you are waiting on

14:20 <_whitenotifier-5> [actions] mithro opened issue #22: Consider renaming actions/checks to actions/basic-checks and converting actions/checks to composite action? - https://git.io/JOgXW

14:51 <sf-slack> <cjearls> Thanks!

16:08 <sf-slack> <dkansagara> Hi i am trying to take my design from VPR(fasm) to vivado, i saw python fpga interchange repository for interchange file generation but i am not sure exactly how it will convert fasm to interchange capncp. i have seen example_netlist.py but it generates the new design rather than taking fasm file as input. convert.py can covert certain file format(yaml,json) to interchange but not fasm

16:16 <sf-slack> <acomodi> Hi @dkansagara. If you have a fasm file generated by VPR you can look at symbiflow-xc-fasm2bels

16:18 <sf-slack> <acomodi> It is able to generate FPGA interchange physical and logical netlists which can then be used to generate a dcp (I am assuming here though that it is an xc7 device)

16:22 <sf-slack> <dkansagara> Hi @acomodi i am trying xc-fasm2bels but not sure about one input argument part *connection_database* it takes as input, i have generated xc7 part device database from rapidwright but not sure is it that conncetion_database it expects , or tilegrid connection database

16:24 <sf-slack> <acomodi> The comment there on the connection database argument may lacks to say that, if no connection database is present at the specified path, it is automatically generated

16:25 <sf-slack> <acomodi> So you have sth like `--connection_database <some_path>/xc7a35t.db`

16:51 <sf-slack> <dkansagara> oh okay got it. Thank you @acomodi

16:52 <_whitenotifier-5> [symbiflow-arch-defs] kkumar23 opened issue #2128: enable CI for the quicklogic testcases added - https://git.io/JO2IK

19:35 <sf-slack> <timo.callahan> Hi @cjearls, yes, symbiflow-examples should work for you -- install the xc7 tools, then to run the examples -- you'll only need to create a new .xdc file for the Nexys A7 (most likely you can search for one from Digilent then edit if necessary). And do some small edits in the example-level Makefile for the new TARGET. Start with counter_test.

19:53 <sf-slack> <cjearls> @timo.callahan Awesome, thanks for the help! Do symbiflow_synth, symbiflow_pack, symbiflow_place, symbiflow_route, symbiflow_write_fasm, and symbiflow_write_bitstream use other projects like Yosys, nextpnr, or vpr? Is the eventual goal to have xilinx equivalents to nextpnr-ecp5, ecppll, and ecppll?

20:10 <tcal> cjearls: Yes, they are just wrappers, so I think with some digging you can figure out what the underlying tools are. Presumably Yosys for synth and pack. And I think the XC7 tools use vpr (also called vtr, "verilog-to-routing") for place and route. The fasm-to-bitstream tool I think is our own.

20:11 <sf-slack> <cjearls> Ok, thanks, that was my understanding

20:11 <sf-slack> <cjearls> I'm still wrapping my head around the project, as there are a lot of moving parts, but I think I'm starting to understand how everything works

20:13 <tcal> Currently I'm using a new variant of Symbiflow, targeting Lattice Crosslink NX --- it uses Yosys and nextpnr-nexus (which in turn uses project Oxide).

20:33 <Lofty> tcal: I wouldn't call Nexus a Symbiflow project

20:33 <Lofty> *Oxide, targeting Nexus

20:48 <tcal> lofty: Thanks, you're right

22:52 <mithro> Lofty: Well my employer (through me) is funding Dave Shah to do Oxide work

22:53 <Lofty> I, uh, probably *wouldn't* deadname someone in public

22:54 <mithro> Sorry, did I miss a name change?

22:54 <Lofty> gatecat.

22:57 <sf-slack> <cjearls> Is there a reason people use usernames instead of their actual names in the open source FPGA community?

22:57 <mithro> Lofty: Oh, I thought it was fpgadave -> gatecat -- didn't realize it was a preferred name change. I apologize if I should no longer be using the other name.

22:59 <Lofty> cjearls: the open source FPGA scene relies on a few incredibly load-bearing trans people to keep functioning. Using usernames makes these things less painful.

23:00 <mithro> cjearls: It's pretty common in much of the open source, some people don't like their real name, some people like being more anonymous

23:00 <Lofty> And, sure, I have a legal name. But to basically everyone in the scene, my name *is* Lofty, and I much prefer it that way.

23:01 <mithro> I started signing things "Tim 'mithro' Ansell" after it turned out that people didn't associate my open source "mithro" with my real world identity "Tim Ansell"

23:02 <mithro> It is a general good idea to use whatever people ask you to use....

23:03 <sf-slack> <cjearls> Thanks for letting me know, I wasn't aware

23:04 <Lofty> mithro: but yeah, gatecat has gone to noticeable effort to change their username everywhere

23:06 <gatecat> yeah, I still don't mind my old name in private but I'm definitely trying to move on from it in public going forward

23:06 <mithro> gatecat: Okay, very happy to use whatever you prefer where you prefer it.

23:07 <gatecat> thanks!