<tcal>
gatecat: I'm getting a large amount of unexpected trimming when synthesizing with Yosys for Nexys, compared to Radiant. Are there any common causes for this I can look for, such as x propagation?
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<gatecat>
tcal: yes, look for disconnected inputs to submodules, these tend to be optimised quite aggressively by Yosys
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<cjearls>
I have the Nexys4DDR LEDs working with the PicoSoC example in symbiflow-examples, but I'm having some difficulty with connecting to UART. The manufacturer XDC file shows 4 pins in the USB-RS232 interface, UART_TXD_IN, UART_RXD_OUT, UART_CTS, and UART_RTS. I've tried the tx and rx pins alone, tried swapping them, and tried setting the CTS and RTS pins to 0 while keeping the tx and rx pins, but I can't seem to connect to the UART with
<cjearls>
"screen /dev/ttyUSB1 460800". Does anyone have any idea what I might be doing wrong?
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<_whitenotifier-3>
[sv-tests] Prahitha opened issue #1469: Keep the first column (tags) fixed on scroll-x - https://git.io/JO6IU
<_whitenotifier-3>
[sv-tests] Prahitha opened issue #1470: add horizontal scroll for the dataTable - https://git.io/JO6I2
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