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<sf-slack>
<cjearls> Is there a place to find yosys optimization strategies? I have a design that is taking up 160% of the logic slices in my orangecrab, and I was hoping to find some yosys settings to reduce the utilization enough that it'll fit
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<tnt>
cjearls: That's not a optimization strategy you need, it's a miracle.
<Lofty>
cjearls: you're running with -abc9 right?
<Lofty>
Also consider -abc9 -dff
<tnt>
I don't have that much faith in abc9 to go from 160% LC usage to something placable/routable.
<tnt>
At that point you need a whole new architecture for whatever you're doing.
<umarcor>
agree. pnr needs to be done. even 80-90% may be difficult to fit.
<Lofty>
tnt: ABC9 and a more accurate delay target can do a *lot* to reduce area
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<tnt>
Huh, I have never seen any such drastic area reduction on any real world design by using abc9. At most I think I've seen 10% LUT reduction which doesn't even translate to 10% LC reduction since a bunch would have been packed with an adjacent FF.
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<sf-slack>
<vastarparaakshar> Kintex-7 support is on the planning?
<Lofty>
tnt: are you setting ABC9 delay targets or just passing "-abc9" and assuming the best?
<tnt>
Lofty: not sure what you mean ... I pretty much always run my designs however fast they'll go.
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<Lofty>
That might be why you're experiencing not much in the way of area reduction
<Lofty>
To people who have other constraints it can help a lot
<tnt>
How do you specify the target frequency ? synth_ecp5 doesn't have anything in help
<Lofty>
It's not a target frequency but target delay in picoseconds, which you pass to -D
<Lofty>
(synth_ecp5 -D)
<Lofty>
I normally turn target frequency to picoseconds then halve it to account for interconnect delay
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<cjearls>
Lofty: I'm getting an unknown option error when running "synth_ecp5 -nowidelut -abc9 -dff -D 80000 -json gsd_orangecrab.json -top gsd_orangecrab" for the -D option, and I can't find it in the synth_ecp5 documentation
<Lofty>
Ah, the joys of Yosys having different options for different flows