06:50 <sf-slack1> <fdarling> Do you know of someone (maybe you?) who'd be willing to get support for the Artix-7 chip on the MicroNova Mercury 2 FPGA if I were to gift them a board?

06:54 <sf-slack1> <fdarling> it wasn't available on SciHub either, so I am guessing (like Chander said) that it isn't in circulation yet

11:13 <sf-slack1> <cjearls> I'd be happy to help add support for it. Is there no support for it at all in SymbiFlow currently, or is there just no example in the symbiflow-examples repo?

13:22 <_whitenotifier-3> [nextpnr] gatecat opened issue #287: [interchange] Site pin conflicts in RAM test - https://git.io/J3atP

15:21 <calphool> Hello all, question: how does timing analysis work with the Symbiflow tool chain?

16:07 <Lofty> calphool: As I understand it both VPR and nextpnr output the critical path

16:14 <sf-slack1> <calphool> My experience is mostly in Quartus. So in there you set timing constraints in the sdc file. Then when you do the place and route you get a timing analysis report where it tells you whether you were able to achieve the constraints you provided, and somehow the tool knows what's achievable across temperature ranges and so on. I was under the impression that that stuff was proprietary to Quartus for its known chip

16:14 <sf-slack1> set. Are those physical characteristics part of what's in the open?

16:15 <calphool> Sorry.. I am running both Slack and IRC... calphool = JR

16:18 <Lofty> So, uh

16:18 <Lofty> Intel stuff comes under Project Mistral, of which I am project lead

16:19 <Lofty> It's not technically a Symbiflow project

16:22 <Lofty> Anyway, the long and short of it is that while they're not in the open, you can obtain that timing information by looking at the output of quartus_sta on a netlist

16:23 <Lofty> And if you correlate these with the paths, you now have path timings

16:44 <umarcor> is it possible to do fine-grained placement with Yosys + nextpnr? i.e. tell which specific BRAM block(s) to use when inferring some memory, and let the tools handle all the rest of the placement and routing.

16:44 <umarcor> the use case is having multiple designs/bitstreams which all share the same specific BRAM block.

16:47 <Lofty> umarcor: https://github.com/YosysHQ/nextpnr/blob/master/docs/constraints.md#absolute-placement-constraints

16:48 <umarcor> Lofty: thanks!

17:27 <mithro> @acomodi: New prjxray-db push with the new DSP pips - https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master

17:31 <mithro> gatecat: Need anything from me regarding the interchange format stuff?

17:32 <gatecat> mithro: you could give https://github.com/SymbiFlow/python-fpga-interchange/pull/80 a review if you want? otherwise I think all is good

17:32 <mithro> calphool - VPR outputs a timing report

17:32 <mithro> calphool: VtR also supports timing constraints -> https://docs.verilogtorouting.org/en/latest/vpr/timing_constraints/

17:33 <tpb> Title: Timing Constraints Verilog-to-Routing 8.1.0-dev documentation (at docs.verilogtorouting.org)

17:33 <mithro> According to https://docs.verilogtorouting.org/en/latest/vpr/debug_aids/ -- The report_timing.setup.rpt file lists details about the critical path of a circuit, and is very useful for determining why your circuit is so fast or so slow.

17:33 <tpb> Title: Debugging Aids Verilog-to-Routing 8.1.0-dev documentation (at docs.verilogtorouting.org)

17:37 <mithro> gatecat: There are a number of BYU students who want to look at graph folding with the interchange format

17:37 <gatecat> mithro: excellent

17:38 <gatecat> I'm happy to answer questions/discuss ideas if they want

17:38 <mithro> gatecat: I've invited Brent (their supervisor) to the interchange format meeting on Thursday morning

22:51 <sf-slack1> <jgoeders> It seems master on https://github.com/SymbiFlow/fasm is broken? I don't see any issue about it, but it's been that way for a while so I thought I would mention it here.

23:28 <sf-slack1> <cjearls> I just ran into the same issue on Ubuntu 20, then saw that the Project X-Ray docs give instructions for Ubuntu 16.04, so I made a virtual machine, and I'm still getting an error when trying to make the environment

23:43 <sf-slack1> <jgoeders> Interestingly when I go back to an older fasm commit that passed CI I seem to be getting the same error. So perhaps some antlr dependency has changed. ...I'm still looking into it.