09:05 <jokus_malus> Hello! I have never worked with FPGAs before, but I would like to dive into that topic and help with SymbiFlow. I was a web developer for several years and work as an embedded developer since a few months. From the list on the website, I know some python and am pretty good with english and docker. Apart from that, I'm good with C, linux and network stuff. Is there a rather small and non-time-critical task I could start

09:05 <jokus_malus> with?

10:49 <_whitenotifier-3> [python-fpga-interchange] gatecat opened issue #81: Allow patching of StringIdx values - https://git.io/J3xbO

10:54 <_whitenotifier-3> [python-fpga-interchange] gatecat opened issue #82: Allow patching of lists - https://git.io/J3xNG

13:55 <sf-slack1> <jgoeders> @mithro You mentioned someone (perhaps at Antmicro?) has created a VTR architecture file for 7-series CLBs. Do you know who this was or where these files live? Thanks!

13:58 <mithro> jgoeders: https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/xc/common/primitives

13:59 <mithro> @jokus_malus -- There is a large amount of optimization work that can be done

14:18 <sf-slack1> <jgoeders> @mithro Thanks. I'll pass this on to my students and we will start looking at this.

15:33 <nickoe> jokus_malus: Are tou familiar with the dymbiflow toolchain. Have you tired out the symbiflow-examples stuff?

19:50 <jokus_malus> nickoe: No, I haven't tried anything yet

19:52 <nickoe> jokus_malus: Maybe that is a good start to get an intro to what it all is a about? And maybe you can find something to contribute via that?