<ZipCPU>
Ever tried placing the files in question on the command line? I can get you the syntax for that if you would like.
* ZipCPU
digs into the icozip project ...
<gurki>
not sure what you mean. stating them explicitely?
<ZipCPU>
No, still using the shell escape
<gurki>
i have a feeling that i should mention that im using windows at this point ...
<ZipCPU>
Here was the command I used: yosys -p 'synth_ice40 -blif icozip.blif -top toplevel' *.v
<ZipCPU>
I'm guessing you should be able to do something like: yosys -s script.ys *.v
<ZipCPU>
I've just ... never tried it.
<gurki>
so i would write the command stated by this guy to get the graph into some file and call that script.ys?
<gurki>
comamnds*
<ZipCPU>
Yes. Put everything into the script with the exception of the read_verilog commands.
<gurki>
ok. will do
<ZipCPU>
Then put the verilog filenames onto the command line.
<ZipCPU>
Please let me know if it works, and what you think of it if so ... I haven't tried the "show" command yet, though I've seen others do so.
<gurki>
ERROR: Can't open input file `*.v' for reading: Invalid argument
<gurki>
hmm
<ZipCPU>
Did you put that in quotes?
<gurki>
yosys -s script.ys *.v
<ZipCPU>
Yeah, that was my thought. That didn't work?
<gurki>
thats the command i tried
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<ZipCPU>
Let me try it myself, without the *.v though ... (I've got a nice demo at hand ...)
<gurki>
could you check whether that *.v works when running linux?
<ZipCPU>
Sure, but let me do one step at a time first.
<gurki>
i dont have a linux with root access at hand so id have to compile yosys on some machine i can ssh to
<gurki>
absolutely :)
<ZipCPU>
Ok, so ... w/o the *.v I got it working. (I can send you the .v file if you'd like ... it was *REALLY* simple)
<ZipCPU>
So, let's see if we can try this on something requiring multiple files ...
<ZipCPU>
Hmm "For formats different than 'ps' or 'dot' only one module must be selected.
<ZipCPU>
Let's see if "prep" will help with that
<gurki>
is this the error you get when using that wildcard?
<gurki>
or are you stating them explicitely right now
* ZipCPU
sighs. There's another spam bot active on IRC.
<ZipCPU>
Hmm ... haven't used the wildcard yet, 'cause the files composing this component are in separate directories.
<ZipCPU>
Let me get it to work with multiple files first ...
<ZipCPU>
Same error ...
<ZipCPU>
Hold on ... let me ask on another channel ...
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<ZipCPU>
Ok, I have a not from the master ;) : for most output formats (including the xdot display) you need to select objects from a single module when your design contains multiple modules.
<gurki>
so what happens when module a uses modules stated somewhere else?
<ZipCPU>
Heh, yeah, ... and my example still isn't working
<ZipCPU>
So, I have a fairly simple example with three parts: two LRS's and a master file on top of them. The master file returns the two LRS's xor'd together.
<ZipCPU>
That's what I'm trying to use at least, while placing the verilog file names on the yosys command line.
<ZipCPU>
I'm not being very successful right now, however.
<awygle>
And what's your desired output?
<awygle>
In the sense of what you expect the graph to look like
<ZipCPU>
My desired output would be a display on the screen.
<ZipCPU>
I actually don't really care what the chart looks like, gurki might for his data, I'm just trying to get a chart.
<awygle>
Do you have xdot installed?
<ZipCPU>
Yes.
<gurki>
awygle: my expected output would be a graph depicting the instances of modules and whatnot used in that project i try to understand atm
<awygle>
I would start with a flow that just reads one file and shows it, to make sure the pipeline works, before adding all the synthesis steps
<gurki>
im aware that this graph is going to be huge for more complicated projects but its still easier to understand whats going on than a whole bunch of verilog files
<gurki>
than using*
<ZipCPU>
Well, I just found one bug ... I was changing one file and executing another ... :|
<ZipCPU>
Ok, I've got a multi-file example working using read_verilog.
<ZipCPU>
I had to plot using postscript, though ... but it shows nicely in gv.
<ZipCPU>
Let's see if I can skip the read_verilog commands and just use the command line now.
<ZipCPU>
Then click on the 2nd lick, the one about resources to improve FPGA skills.
<ZipCPU>
PiasaChimera commends in response to DillonHuff, "There are a few coding style guidelines out there. A lot of time they are based on incomplete support by synthesis tools. Or based upon synthesis tool issues. ...."
* awygle
goes on a ten minute rant about a reusable verilog frontend
<gurki>
oh well.
* awygle
's cats are very confused
<gurki>
:D
<ZipCPU>
Lol
<awygle>
gurki: if you can spare the time to produce a minimum example of the issue, it might actually be fixed
<ZipCPU>
still lol'ing
<awygle>
Unless it's a non-synthesizable construct
<ZipCPU>
Or, perhaps, a minimal example of "each" issue ...
<ZipCPU>
I think it's mostly about tasks, right, gurki?
<awygle>
ZipCPU: point :-P
<awygle>
What even are tasks? I've never used them
<gurki>
not mine. i actually just want to port hermes-lite to a zedboard. but this guy already did some of the pita work and threw a lot of bloat away
<gurki>
"just" <- lol
<awygle>
They have to be square apparently
<ZipCPU>
Clifford is very responsive to my "Issues", however. Post an issue to yosys on github, and you'll get a response within a day or two.
<awygle>
Based on a quick Google
<awygle>
Until system verilog, which quartus supports
<gurki>
ERROR: Parser error in line ad9866.v:35: syntax error, unexpected TOK_REG
<awygle>
Clifford is very responsive to *good* bug reports. I think he gets an excess of THIS DOESN'T WORK MAKE IT WORK
<gurki>
- using read_verilog -sv
<gurki>
well i am already at do d to c to b to do a which is what i actually want to do :(
<gurki>
this mess of deign tools is frustrating
<gurki>
design*
<gurki>
not flaming yosys here. its a problem of the hdl world.
<ZipCPU>
What was awygle telling his cats about front ends again?
<gurki>
:P
<awygle>
I'm at the point of the rant where I piss off the Migen people by saying we shouldn't waste time on bespoke HDLs when we don't even have useful implementations of the standard ones
<gurki>
its all a mess, really
<ZipCPU>
Care to join me using autofpga then? :P
<gurki>
things become even more fun once you dig into mixed signal simulation tools
<gurki>
as in combine all the fun with spice/veriloga
<gurki>
=[
<awygle>
Truth
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<gurki>
clash actually seemed quite interesting apart from me being a noob at haskel
<awygle>
Everything is awful, every time I use anything I want to recreate it in a less terrible way, but that's infinite work and I'm usually not qualified
<gurki>
nobody is qualified
<gurki>
thats part of the problem
<gurki>
everyone is just messing around with what he has or knows.
<ZipCPU>
You realize ... even Clifford wasn't qualified to write yosys ...
<awygle>
Someday I'm gonna write a PCB EDA tool
<ZipCPU>
At least, that's what they told him before he wrote it.
<awygle>
Yeah I know. It's not the implementation that's the problem (usually), it's that I don't understand the problem domain well enough
<awygle>
Also see above re: infinite work
<ZipCPU>
Heh, yeah ... but when you get old and crusty like me, you've then learned enough problem domains to be critical of how well (or actually poorly) others do them.
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<gurki>
good news! i just got this ad9866.v to synthesize using vivado! :)
<awygle>
congrats :)
<gurki>
thx :)
<ZipCPU>
gurki: That's a good start. Now see if you can get it to synthesize with yosys! :D
<gurki>
ZipCPU: i did not say i was able to generate a bitstream :P
<gurki>
but then these are problems i know how to deal with :)
<ZipCPU>
gurki: I also just learned what I was missing before in how to show just a particular component within a design.
<ZipCPU>
Oh, and ... yosys does work with Xilinx series 7 devices. You can use it to create an EDIF file, which you can then do P&R on.
<ZipCPU>
The only problem is ... it doesn't (yet) handle the DSP elements, so hard multiplies still require some work.
<gurki>
well tbh i just wanted to use yosys as a "general purpose overview genertor"
<gurki>
i dont see a benefit of a free fpga toolchain unless it can actually target both altera and xilinx ...
<gurki>
because id have all that porting pita anyway but a possibly not-quite-as-good tool
<gurki>
still been quite happy when i read that ccc talk announcement :)
<gurki>
mb we will have a vendor agnostic tool some day
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<ZipCPU>
gurki: yosys can synthesize for both altera and xilinx.
<ZipCPU>
... and iCE40
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