clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
pepijndevos has quit [Quit: ZNC 1.6.2 - http://znc.in]
pie_ has quit [Remote host closed the connection]
pie__ has joined #yosys
pie__ has quit [Quit: Leaving]
srk has quit [Quit: ZNC - http://znc.in]
pie_ has joined #yosys
srk has joined #yosys
_whitelogger_ has joined #yosys
danieljabailey has quit [Ping timeout: 240 seconds]
danieljabailey has joined #yosys
digshadow has quit [Ping timeout: 248 seconds]
andi- has joined #yosys
m_w has quit [Quit: Leaving]
digshadow has joined #yosys
digshadow has quit [Ping timeout: 240 seconds]
digshadow has joined #yosys
proteusguy has quit [Ping timeout: 252 seconds]
pie_ has quit [Ping timeout: 248 seconds]
proteusguy has joined #yosys
proteusguy has quit [Ping timeout: 248 seconds]
promach_ has joined #yosys
promach_ has quit [Client Quit]
proteusguy has joined #yosys
pie_ has joined #yosys
_whitelogger has joined #yosys
pie_ has quit [Ping timeout: 260 seconds]
proteusguy has quit [Ping timeout: 248 seconds]
proteusguy has joined #yosys
eduardo__ has quit [Ping timeout: 248 seconds]
eduardo__ has joined #yosys
eduardo_ has joined #yosys
eduardo__ has quit [Ping timeout: 264 seconds]
m_t has joined #yosys
pie_ has joined #yosys
pie_ has quit [Ping timeout: 240 seconds]
johnwhitlow[m] has left #yosys ["Kicked by @appservice-irc:matrix.org : idle on matrix for more than 30 days"]
quigonjinn has quit [Ping timeout: 240 seconds]
proteusguy has quit [Ping timeout: 252 seconds]
pie_ has joined #yosys
proteus-guy has quit [Remote host closed the connection]
proteus-guy has joined #yosys
pie__ has joined #yosys
AlexDaniel has quit [Ping timeout: 240 seconds]
<ZipCPU> Hey, this is cool! I just rebuilt my highly constrained ZipCPU on a Spartan S6/LX4 design after doing a *lot* of formal work on the components.
<ZipCPU> The result? After using 100% (2400/2400 LUTs) on the last (before formal) build, I'm now using 2339 LUTs and *everything* passes timing on the first try!
<ZipCPU> My conclusion? Using formal hasn't hurt me at all. ;)
<awygle> Hearing about running the ZipCPU on these constrained systems makes me wonder where all the LUTs go in something like a Virtex 7
<awygle> it's obviously a very different situation of course, but still
<ZipCPU> awygle: Not sure I follow. What do you expect would be different? That they'd be small crumbs on a table of steaks?
<awygle> just that the ZipCPU built for an LX4 is a different beast than... well, whatever application requires a Virtex 7
<awygle> very high speed networking maybe?
<awygle> it just strikes me funny when i see you talking about using 2339 LUTs and the smallest Virtex 7 has 582,720 "logic cells"
<ZipCPU> awygle: Ok, makes sense, but that was actually part of the purpose of the ZipCPU.
<ZipCPU> Imagine you purchased your Virtex-7 for ... some big hungry processing, and only later discovered you needed a CPU after your FPGA was already crowded with logic.
<ZipCPU> That was my raison d'etre for the ZipCPU.
<ZipCPU> I mean, does it really make sense to make a high-power CPU on an FPGA board? If you wanted a high power CPU, why wouldn't you just buy one
<ZipCPU> ?
<awygle> a question i rarely ask in FPGA IRC, since building one seems to be a favored passtime... ;)
<ZipCPU> I mean ... an FPGA is an awesome package for building a CPU, and a large Virtex-7 would be nice for trying to build a piece of something that might compete with an iCore CPU, but ...
<ZipCPU> I don't have that kind of $$.
<ZipCPU> Neither do I think a young, new, upstart like me would be able to play in that market without years of experience.
<awygle> i honestly find CPUs among the least interesting applications of FPGAs
<awygle> i'm glad others enjoy them but it sort of baffles me *shrug*
<ZipCPU> They have their purpose.
<awygle> almost all my FPGA work (limited though it has been) has been a lot more dataflow-oriented
<ZipCPU> My background is certainly more signal processing oriented, and DSP tends to be data flow oriented.
<ZipCPU> However, some things just don't fit into that model very well.
<ZipCPU> For example, the negotiations necessary to fire up an SD card to store data into.
<ZipCPU> For example, power sequencing
<ZipCPU> For example, network communication
<ZipCPU> For example, the start up and configuration sequences for a whole variety of different chips
<ZipCPU> Sure, you could place all that in logic, but then you'd be using lots of logic that you'd only use once. Alternatively, you could place a CPU on board and share that logic between different CPU programs.
<awygle> that does make sense. although i'd probably argue about network communication - seems pretty dataflowy to me
<awygle> there's obviously some tipping point where all the positive CPU factors (reuse, ease of development, etc) cause it to become superior to small bespoke state machines
<ZipCPU> It does, until you start adding ARP's, PING's, and TCP NACKS, etc.
quigonjinn has joined #yosys
sklv1 has quit [Ping timeout: 272 seconds]
sklv1 has joined #yosys
AlexDaniel has joined #yosys
sklv1 has quit [Ping timeout: 272 seconds]
sklv has joined #yosys
ZipCPU|Laptop has joined #yosys
gnufan has joined #yosys
ZipCPU|Laptop has quit [Ping timeout: 265 seconds]
m_t has quit [Quit: Leaving]
gnufan has quit [Quit: Leaving.]