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<ZipCPU>
Hey, this is cool! I just rebuilt my highly constrained ZipCPU on a Spartan S6/LX4 design after doing a *lot* of formal work on the components.
<ZipCPU>
The result? After using 100% (2400/2400 LUTs) on the last (before formal) build, I'm now using 2339 LUTs and *everything* passes timing on the first try!
<ZipCPU>
My conclusion? Using formal hasn't hurt me at all. ;)
<awygle>
Hearing about running the ZipCPU on these constrained systems makes me wonder where all the LUTs go in something like a Virtex 7
<awygle>
it's obviously a very different situation of course, but still
<ZipCPU>
awygle: Not sure I follow. What do you expect would be different? That they'd be small crumbs on a table of steaks?
<awygle>
just that the ZipCPU built for an LX4 is a different beast than... well, whatever application requires a Virtex 7
<awygle>
very high speed networking maybe?
<awygle>
it just strikes me funny when i see you talking about using 2339 LUTs and the smallest Virtex 7 has 582,720 "logic cells"
<ZipCPU>
awygle: Ok, makes sense, but that was actually part of the purpose of the ZipCPU.
<ZipCPU>
Imagine you purchased your Virtex-7 for ... some big hungry processing, and only later discovered you needed a CPU after your FPGA was already crowded with logic.
<ZipCPU>
That was my raison d'etre for the ZipCPU.
<ZipCPU>
I mean, does it really make sense to make a high-power CPU on an FPGA board? If you wanted a high power CPU, why wouldn't you just buy one
<ZipCPU>
?
<awygle>
a question i rarely ask in FPGA IRC, since building one seems to be a favored passtime... ;)
<ZipCPU>
I mean ... an FPGA is an awesome package for building a CPU, and a large Virtex-7 would be nice for trying to build a piece of something that might compete with an iCore CPU, but ...
<ZipCPU>
I don't have that kind of $$.
<ZipCPU>
Neither do I think a young, new, upstart like me would be able to play in that market without years of experience.
<awygle>
i honestly find CPUs among the least interesting applications of FPGAs
<awygle>
i'm glad others enjoy them but it sort of baffles me *shrug*
<ZipCPU>
They have their purpose.
<awygle>
almost all my FPGA work (limited though it has been) has been a lot more dataflow-oriented
<ZipCPU>
My background is certainly more signal processing oriented, and DSP tends to be data flow oriented.
<ZipCPU>
However, some things just don't fit into that model very well.
<ZipCPU>
For example, the negotiations necessary to fire up an SD card to store data into.
<ZipCPU>
For example, power sequencing
<ZipCPU>
For example, network communication
<ZipCPU>
For example, the start up and configuration sequences for a whole variety of different chips
<ZipCPU>
Sure, you could place all that in logic, but then you'd be using lots of logic that you'd only use once. Alternatively, you could place a CPU on board and share that logic between different CPU programs.
<awygle>
that does make sense. although i'd probably argue about network communication - seems pretty dataflowy to me
<awygle>
there's obviously some tipping point where all the positive CPU factors (reuse, ease of development, etc) cause it to become superior to small bespoke state machines
<ZipCPU>
It does, until you start adding ARP's, PING's, and TCP NACKS, etc.
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