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<vinny>
Hi all. When performing tech mapping, is there a manner to map to a set of gates (e.g. only NOT and OR gates)?
<vinny>
I read about the library file. Would a custom library file help with this issue?
<ZipCPU>
promach: I managed to get your code to work. Instead of looking up shiftreg[(A)-cnt] and testing the result, I created an index wire, wire [3:0] stop_loc, and assigned this wire to
<ZipCPU>
be (A)-loc. The test of assert(shift_reg[stop_loc]==1'b1) then works.
<ZipCPU>
vinny, Welcome to the channel.
<vinny>
Thank you @ZipCPU
<ZipCPU>
vinny: Are you sure there isn't a technology map yet for what you want to do? There are not only iCE40 maps, Xilinx maps, Altera maps, and ASIC maps.
<ZipCPU>
Oh, and I forgot the AIGER map, SMT2 map, and ... there's a couple more.
<ZipCPU>
Is there something you wish to do that isn't captured by these maps?
<vinny>
Where can I locate these tech maps?
<vinny>
Also, how do I envoke them in the executable?
<ZipCPU>
Have you tried running just "yosys", and then typing help?
<ZipCPU>
At the bottom of the help file are a list of commands: write_aiger, write_blif, write_btor, etc.
<ZipCPU>
Further up, you can also see some commands synth_coolrunner2, synth_easic, synth_gowin, synth_greenpak4, etc.
<ZipCPU>
But, that's not quite the question you asked.
<ZipCPU>
You asked where you could locate the techmaps.
<ZipCPU>
For that, let me ask, do you have a copy of the yosys source tree available to you?
<vinny>
yes.
<ZipCPU>
Have you looked in the techlibs directory?
<vinny>
I use the executable. But I downloaded the techmap
<vinny>
err. I downloaded the source code to analyze the issue I have for the techmap
<ZipCPU>
There are also techmaps in the share directory.
<ZipCPU>
However, I'm a touch confused at this point ... am I getting you closer, or can you tell me more of what you are looking for and not finding?
<vinny>
I would like to perform techmap for a custom sets of gates. Eg. A set consisting of NOT and OR, or a set consisting with NOR.
<vinny>
I read that techmap can uses library file to define the target architecture that you wish to map for.
<vinny>
I would like to know how I can complete this task with the library file.
<ZipCPU>
clifford: Are you available to help here?
<ZipCPU>
While I've looked through his code somewhat, and pretended I understood things at various points, he still knows his code better than I do.
<vinny>
ok. I am using the executable, I did not compile the code.
<ZipCPU>
So, the executable has commands defined within it that prep the code for a particular tech map, and then map it and write the results out.
<vinny>
yup. I saw that in the code.
<vinny>
I suppose that I can edit the master library file.
<vinny>
I noticed that there is no NOR gate.
<vinny>
Is it easy to add that gate?
<ZipCPU>
I haven't personally done it, so I'm not sure I could answer that question.
<ZipCPU>
I know there are those who do so fairly easily, but I've got to believe the devil is in the details.
<vinny>
I see.
<vinny>
I will look into this further.
<ZipCPU>
Sorry I couldn't be of any more help.
<vinny>
I will stay logged on in the likelyhood that clifford sees this thread.
<vinny>
otherwise, I will be back tomorrow.
<vinny>
No worries. thank you.
<ZipCPU>
Understand timezones.
<ZipCPU>
It's *very* late at night for Clifford. I know he's usually up late, but I'll be a pumpkin within an hour or two.
<vinny>
lol. ok. thanks.
<vinny>
what time zone is clifford in?
<ZipCPU>
I guess my point is, I wouldn't expect much for the next 12 hrs or so.
<ZipCPU>
IIRC, he's in Germany.
<ZipCPU>
So ... I think it's 3AM there now.
<vinny>
ok. thanks.
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<vinny>
I will ping clifford tomorrow. I did not have much luck.
<vinny>
I found the techmap.v in the techlibs/common folder
<vinny>
I modified a few items in the file, but no luck.
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<ZipCPU>
Yes.
<promach_>
ZipCPU: ??
<ZipCPU>
Yes.
<promach_>
Could you paste the relevant log ?
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<ZipCPU>
promach: I managed to get your code to work. Instead of looking up shiftreg[(A)-cnt] and testing the result, I created an index wire, wire [3:0] stop_loc, and assigned this wire to
<ZipCPU>
<ZipCPU> be (A)-loc. The test of assert(shift_reg[stop_loc]==1'b1) then works.
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<newb_>
hello, anyone used upduino here?
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<ZipCPU>
Welcome to the channel, newb_! Although ... I haven't used upduino.
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<newb_>
ZipCPU: thanks
<newb_>
ZipCPU: do you know why the iceprog is using gpio (on rpi) to program the spi? instead of using linux userspace spidev driver
<ZipCPU>
No. I don't. I guess I just used it without question.
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