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13:35
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ravenexp >
what's the best way to extract docstrings from verilog sources?
13:36
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ravenexp >
there's doxygen-verilog fork, but its output quality is terrible and it crashes in random places
13:38
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ravenexp >
then there's Verilog::Perl, but it requires some programming
13:39
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ravenexp >
maybe yosys has some features wrt. meta commant extraction?
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20:06
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mattvenn_ >
ZipCPU - you around? I'm working through the digi pll example and have a question
20:07
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mattvenn_ >
why do you need an else if condition? why not just use else?
20:07
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mattvenn_ >
and might not using the else if result in an unintended latch?
20:07
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mattvenn_ >
(without the else)
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mattvenn_ >
I also get an error when trying to test your code - sdpll.v:103: error: reg phase_err; cannot be driven by primitives or continuous assignment.
20:50
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mattvenn_ >
I changed it to a reg and use an always block to assign it
20:50
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mattvenn_ >
sorry, it was a reg - I put it in an always block to assign it instead of the assign = in your code
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mattvenn_ >
gotta go, back on Monday
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