clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<vinny> I most likely missed clifford again. I will check back in tomorrow.
<vinny> I need to align the time difference ;-)
<vinny> When is Clifford generally available? Please let me know the time (+time zone)
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<awygle> vinny: honestly I've never seen Clifford in this channel, you might have better luck on twitter or github
<awygle> That said I'm pretty sure he's in UTC+1
<vinny> ok. thanks @awygle.
<vinny> Does he answer threads on stackoverflow or else\where?
<vinny> elsewhere*
<awygle> Yes, and is also fairly active on /r/yosys on reddit
<awygle> vinny: ^
<vinny> Thanks, I may post there.
<vinny> BTW, anygle, Would you know how to enable the techmap stage to only produce nodes of selected gates (e.g. NOT and OR)?
<vinny> awygle*
<awygle> Not off the top of my head, sorry. I feel like a liberty file might be the way to go but I can't do more than suggest that as a research topic
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<vinny> no worries. thanks.
<cr1901_modern> clifford: I'm trying to prove two modules equivalent using equiv_* commands. It fails- can I get yosys to print out an example trace for why it failed?
<cr1901_modern> erm, well just an example waveform, so I can examine why it failed*
<cr1901_modern> https://github.com/cr1901/triport-test/blob/master/yosys/induct.ys Everything's set up in an MCVE, btw (MCVE in the sense that "don't read the triport*.v files. Pretend they're magic boxes.)
<cr1901_modern> hmmm I really probably should've just tried selecting the relevant nets from lm32 for this, rather than trying to make an entire new file with the logic I need extracted.
<cr1901_modern> I wonder if yosys can select _just_ the nets I need _and_ create a new module by inferring ports from "the selected nets which don't connect to anything".
<cr1901_modern> "Warning: No SAT model available for cell reg_0_gate (lm32_ram)." Wonder why... ah well, I'll figure it out tomorrow.
<cr1901_modern> clifford: Context: I want to see whether some very specific code for instantiating a block RAM matches how yosys will infer a block RAM.
<cr1901_modern> I'm a bit worried b/c yosys doesn't actually generate net-for-net (i.e. structurally?) equivalent boilerplate code for interfacing to an ICE40 block RAM as the boilerplate present in explicit instantiation.
<cr1901_modern> So I want to prove they are in fact equivalent for peace of mind :D!
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<ZipCPU> cr1901_modern: Did you have an MVCE set up?
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<vinny> clifford: I have a question in regards to assigning the node to a set of Gates. How would I use yosys to make tech mapping produce node with only NORs?
<vinny> I created a liberty file and applied it to abc but I was unsuccessful. I also create a techmap file (-map) but I and unsuccessfull as well.
<vinny> I assume the latter approach is due to incorrectly formatting the file.
<vinny> Any help or direction would be appreciated. Thanks
<cr1901_modern> ZipCPU: https://github.com/cr1901/triport-test "make induct"
<cr1901_modern> Go wild and have fun, I'm taking a break from it
<ZipCPU> vinny: Still around?
<vinny> yes
<ZipCPU> I have instructions for you. ;)
<vinny> What's up ZipCPU
<vinny> awesome thanks
<ZipCPU> Use the yosys "abc" command, such as yosys -p 'synth -top toplevel_module_name; abc -g OR' toplevel_module_name.v
<ZipCPU> That will build your project using OR and NOR gates alone.
<ZipCPU> Hopefully that answers your question.
<ZipCPU> The ABC tool within yosys can also be used to build designs using any number of primitive gate types.
<ZipCPU> The idea is, you should be able to list the primitive gates of interest in the abc command line.
<vinny> if there are more than one gate, how do I separate them?
<ZipCPU> What do you mean?
<vinny> synth -top toplevel_module_name; abc -g OR -g NOT
<vinny> another parameter for -g argument
<ZipCPU> Ahh ... separate them with commas, such as: abc -g OR,NOT
<vinny> ok. I'm going to try that now. Thank you.
<vinny> :-)
<ZipCPU> However, the "NOT" gate comes for free with the "OR" gates alone, so you don't need to specify it.
<vinny> I get an error with the -g argument
<ZipCPU> Really?
<vinny> ERROR: Command syntax error: Unknown option or option in arguments. > abc -g OR > ^
<ZipCPU> I just tested that earlier today.
<vinny> I'm using a build in the repo
<ZipCPU> You mean ... as opposed to building from git?
<vinny> Ubuntu* repo
<vinny> would it be in the latest commit?
<ZipCPU> It was the latest commit that I tested with.
<vinny> ok. I will try to build the latest commit
<vinny> is there a manner to complete my task without abc?
<ZipCPU> Could be. If there is, I don't know about it. (I just found out about using abc for this purpose today as it is.)
<vinny> okay. thank you.
<vinny> I will try to build the latest commit
<ZipCPU> ;)
<ZipCPU> cr1901_modern: Looking over your code, the exact details of what you are doing aren't readily apparent.
<ZipCPU> (This was Clifford's comment when he looked at your code earlier as well ...)
<ZipCPU> I have ran the code, and I see that equivalence fails--four cells being less than equivalent.
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