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<vinny>
I most likely missed clifford again. I will check back in tomorrow.
<vinny>
I need to align the time difference ;-)
<vinny>
When is Clifford generally available? Please let me know the time (+time zone)
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<awygle>
vinny: honestly I've never seen Clifford in this channel, you might have better luck on twitter or github
<awygle>
That said I'm pretty sure he's in UTC+1
<vinny>
ok. thanks @awygle.
<vinny>
Does he answer threads on stackoverflow or else\where?
<vinny>
elsewhere*
<awygle>
Yes, and is also fairly active on /r/yosys on reddit
<awygle>
vinny: ^
<vinny>
Thanks, I may post there.
<vinny>
BTW, anygle, Would you know how to enable the techmap stage to only produce nodes of selected gates (e.g. NOT and OR)?
<vinny>
awygle*
<awygle>
Not off the top of my head, sorry. I feel like a liberty file might be the way to go but I can't do more than suggest that as a research topic
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<vinny>
no worries. thanks.
<cr1901_modern>
clifford: I'm trying to prove two modules equivalent using equiv_* commands. It fails- can I get yosys to print out an example trace for why it failed?
<cr1901_modern>
erm, well just an example waveform, so I can examine why it failed*
<cr1901_modern>
hmmm I really probably should've just tried selecting the relevant nets from lm32 for this, rather than trying to make an entire new file with the logic I need extracted.
<cr1901_modern>
I wonder if yosys can select _just_ the nets I need _and_ create a new module by inferring ports from "the selected nets which don't connect to anything".
<cr1901_modern>
"Warning: No SAT model available for cell reg_0_gate (lm32_ram)." Wonder why... ah well, I'll figure it out tomorrow.
<cr1901_modern>
clifford: Context: I want to see whether some very specific code for instantiating a block RAM matches how yosys will infer a block RAM.
<cr1901_modern>
I'm a bit worried b/c yosys doesn't actually generate net-for-net (i.e. structurally?) equivalent boilerplate code for interfacing to an ICE40 block RAM as the boilerplate present in explicit instantiation.
<cr1901_modern>
So I want to prove they are in fact equivalent for peace of mind :D!
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<ZipCPU>
cr1901_modern: Did you have an MVCE set up?
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<vinny>
clifford: I have a question in regards to assigning the node to a set of Gates. How would I use yosys to make tech mapping produce node with only NORs?
<vinny>
I created a liberty file and applied it to abc but I was unsuccessful. I also create a techmap file (-map) but I and unsuccessfull as well.
<vinny>
I assume the latter approach is due to incorrectly formatting the file.
<vinny>
Any help or direction would be appreciated. Thanks