<tpb>
Title: SystemVerilog, VHDL, SVA SymbiYosys 0.1 documentation (at symbiyosys.readthedocs.io)
<emily>
I think you can do some SystemVerilog stuff with just the free software toolchain, though I'm not 100% certain on that.
citypw has joined #yosys
<mkru>
The more I read, the more I get a feeling that SymbiYosys is just a marketing product, not an open source tool. To use it in a big, complex projects you still need to buy licenses.
<emily>
I think there's the intention to improve SystemVerilog support in the all-Free toolchain, it just needs someone to actually put in the work
<emily>
rebuilding entire commercial toolchains that have had decades to develop and mature from the ground up isn't easy
<mkru>
emily: Does it require improvements in frontend, backend or both? Do you know?
<emily>
the frontend would definitely need work; I've heard talk about adding more common SV features being blocked on some parser troubles or something? But I'm really not the person to ask, I'm still an amateur and haven't used SV at all yet ^^;
<emily>
there's also ##openfpga btw, where azonenberg is talking about adding SystemVerilog features to yosys right now in fact
proteusguy has quit [Ping timeout: 276 seconds]
<ZipCPU>
mkru: @(posedge clk) and @(negedge clk) are both supported by FOSS yosys .... ;)
<tnt>
lol
<tnt>
negedge should definitely be a premium feature, who needs that ...
<ZipCPU>
mkru: I've been through the parser a couple times. It works, but there's discussion that it could use a rewrite. To my knowledge, no one is working on that
<ZipCPU>
I'm not sure if the native parser would be up to SystemVerilog
<ZipCPU>
That said, I've looked over many of the missing features and there's been more than once when I seriously thought of adding them in
<ZipCPU>
For example, $onehot and $onehot0 would be valuable to me, and not all that hard to add in
<mkru>
I would like to contribute but C++ is a big issue for me.
<mkru>
I wish I could use Rust.
<ZipCPU>
I'd also like to be able to do simple single-clock SVA assertions: assert property (@(posedge i_clk) disable iff (A) B |=> C); Those shouldn't be so hard, but been busy enough with other projects that I haven't dug into that
<ZipCPU>
IIRC, Clifford committed to implementing the dot notation, and if you look hard enough you'll find some support for it
Kergadon has quit [Quit: Leaving]
<ZipCPU>
One of the issues was associated with finding the width and the type of the sub-module value
<ZipCPU>
The bottom line, however, is that all this work costs money and ... unless someone ponies up to pay for it, the paying customers will get all the support
<ZipCPU>
I know there was one customer who was going to fund a full SystemVerilog back end, but then dropped out before the agreement could be finalized
<ZipCPU>
I also know there are several folks working on integrating various VHDL back ends ... those might become useful soon enough
<ZipCPU>
Sorry, VHDL front ends, not back ends
<ZipCPU>
The biggest problem I've heard from the VHDL front ends is that simple/basic support is easy to do, but no one has invested the time to get full feature support
<mkru>
Actually, what is front end responsible for and what is back end responsible for? Verilog has both.
<daveshah>
The front end reads and elaborates Verilog into Yosys' internal representation (RTLIL), the backend writes that out as Verilog
<daveshah>
Only the front end would need significant work for SystemVerilog (for the most part SV features would be lost during elaboration anyway, so there would be no changes to what the backend needs to write)
<hackerfoo>
There is effort on open source SystemVerilog support, but it will take time.
<hackerfoo>
If anyone wants to contribute, let us know on #symbiflow. We could use some help :)
<mkru>
Are you the owner?
<hackerfoo>
mithro is the lead. I've been working on the project since April.
<hackerfoo>
(SumbiFlow, not sv2v)
<hackerfoo>
*SymbiFlow
<mkru>
What do you focus your work right now?
<mkru>
on*
<hackerfoo>
I'm working on Xilinx 7 series support.
<hackerfoo>
We're working towards Linux on a SoC on an Artix 7.
<mkru>
Sounds nice. Do you have any topics, that sounds like potential PhD thesis?
<hackerfoo>
mkru: I'm sure I could help you find one. We're using Verilog to Routing (https://verilogtorouting.org/), which is used in academic research.
adjtm has quit [Ping timeout: 276 seconds]
ZipCPU has quit [Excess Flood]
ZipCPU has joined #yosys
adjtm has joined #yosys
rohitksingh has joined #yosys
emeb has joined #yosys
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined #yosys
chipb has quit [Ping timeout: 246 seconds]
adjtm has quit [Remote host closed the connection]
chipb has joined #yosys
adjtm has joined #yosys
dys has quit [Ping timeout: 245 seconds]
adjtm has quit [Remote host closed the connection]
cr1901_modern has quit [Ping timeout: 240 seconds]
adjtm has joined #yosys
dys has joined #yosys
rohitksingh has quit [Ping timeout: 240 seconds]
cr1901_modern has joined #yosys
dys has quit [Ping timeout: 276 seconds]
dys has joined #yosys
dys has quit [Ping timeout: 240 seconds]
proteusguy has quit [Ping timeout: 246 seconds]
rohitksingh has joined #yosys
rohitksingh has quit [Ping timeout: 246 seconds]
<mithro>
mkru: plenty of potential PhD thesis projects
<mithro>
mkru: if your interested, happy to work with you to find something which matches your and your unis interests
dys has joined #yosys
rohitksingh has joined #yosys
dys has quit [Ping timeout: 245 seconds]
phire has quit [Ping timeout: 264 seconds]
forksand has joined #yosys
proteusguy has joined #yosys
mkru has quit [Remote host closed the connection]
MrBismuth has joined #yosys
MrBusiness3 has quit [Ping timeout: 276 seconds]
rohitksingh has quit [Ping timeout: 240 seconds]
mkru has joined #yosys
rohitksingh has joined #yosys
shorne has quit [Ping timeout: 258 seconds]
shorne has joined #yosys
mkru has quit [Read error: Connection reset by peer]
mkru has joined #yosys
adjtm has quit [Ping timeout: 276 seconds]
rohitksingh has quit [Ping timeout: 245 seconds]
ZipCPU is now known as ZipCPU|AFK
adjtm has joined #yosys
mkru has quit [Remote host closed the connection]
rohitksingh has joined #yosys
rohitksingh has quit [Ping timeout: 245 seconds]
pie_ has quit [Ping timeout: 240 seconds]
rohitksingh has joined #yosys
rohitksingh has quit [Ping timeout: 240 seconds]
rohitksingh has joined #yosys
emeb_mac has joined #yosys
rohitksingh has quit [Ping timeout: 245 seconds]
pie_ has joined #yosys
rohitksingh has joined #yosys
rohitksingh has quit [Remote host closed the connection]
rohitksingh has joined #yosys
s_frit has quit [Remote host closed the connection]