MrBismuth has quit [Read error: Connection reset by peer]
<promach>
I mean how do I interface synth output from yosys to nextpnr-ice40 ?
<daveshah>
`synth_ice40 -json out.json`
<promach>
daveshah : thanks. By the way, how to remove all ice40 DFF in the case of using ltp command ?
<promach>
I mean for synth_ice40
<promach>
it is ltp t:$_DFF_P_ %n for synth
<daveshah>
ltp t:SB_DFF* %n
<promach>
daveshah: what about for synth_ice40 ?
<promach>
Thanks, let me try
<promach>
ERROR: failed to place cell '$abc$80826$auto$blifparse.cc:492:parse_blif$84024_LC' of type 'ICESTORM_LC'
<promach>
Placing design failed.
<promach>
daveshah : I had this place error in nextpnr
<daveshah>
Is your design over utilised?
<promach>
Number of wires: 6514
<promach>
Number of wire bits: 14957
<promach>
Number of public wires: 1168
<promach>
Number of public wire bits: 9091
<promach>
Number of memories: 0
<promach>
Number of memory bits: 0
<promach>
Number of processes: 0
<promach>
Number of cells: 8769
<promach>
SB_CARRY 400
<promach>
SB_DFF 232
<promach>
SB_DFFE 432
<promach>
SB_DFFESR 1968
<promach>
SB_DFFESS 40
<promach>
SB_DFFSR 248
<promach>
SB_LUT4 5449
<promach>
I am trying to fit into tinyFPGA BX
<promach>
the previous error was for lattice 1k FPGA
<promach>
the error below is for tinyFPGA BX
<promach>
ERROR: failed to place cell 'data_input[21]$sb_io' of type 'SB_IO'
<promach>
Placing design failed.
<promach>
daveshah:
<daveshah>
Sounds like you have too many IO pins
<promach>
does this mean pins overuse
<promach>
ok
cr1901_modern has quit [Ping timeout: 240 seconds]
pie_ has quit [Ping timeout: 240 seconds]
cr1901_modern has joined #yosys
GoldRin has joined #yosys
chipb has quit [Ping timeout: 268 seconds]
pie_ has joined #yosys
GoldRin has quit [Ping timeout: 276 seconds]
cr1901_modern has quit [Quit: Leaving.]
somlo has quit [Ping timeout: 244 seconds]
chipb has joined #yosys
somlo has joined #yosys
cr1901_modern has joined #yosys
emeb has joined #yosys
dys has joined #yosys
cr1901_modern has quit [Quit: Leaving.]
Jybz has quit [Quit: Konversation terminated!]
citypw has quit [Ping timeout: 276 seconds]
indy has joined #yosys
cr1901_modern has joined #yosys
<ZirconiumX>
wq: Idea for bugpoint - a -grep-like argument for "interesting" crashes. For example, you might ask it to bugpoint an assert on a specific line, but dump anything which contains the phrase "ERROR: Assert"
<janrinze>
number of cells seems too much too..
<daveshah>
That's cells from a Yosys point of view. Some carries LUTs and DFFs will pack together
Max-P has quit [Quit: SIGSEGV]
Max-P has joined #yosys
<janrinze>
daveshah: the ecp5 board you were working on, is that available somewhere?
<daveshah>
No, I'm afraid it isn't
<janrinze>
it's like the versa but has hdmi and such, right?
<daveshah>
It might be at some point in the future depending on how things work out
<janrinze>
perhaps i should look into designing a daughterboard for the eval board from lattice
rohitksingh has joined #yosys
Jybz has joined #yosys
pie_ has quit [Ping timeout: 245 seconds]
rohitksingh has quit [Ping timeout: 240 seconds]
rohitksingh has joined #yosys
pie_ has joined #yosys
rohitksingh has quit [Ping timeout: 265 seconds]
<janrinze>
daveshah: is there a tool to modify the BRAM in a ecp5 design like with ice40?
<daveshah>
No, there isn't
<daveshah>
Exactly the same concept could be used though
rohitksingh has joined #yosys
<janrinze>
ECP5 support is relatively new, isn't it?
<janrinze>
or has a lot smaller user base?
<daveshah>
About a year old
<daveshah>
Compared to 4 years for iCE40
<janrinze>
makes sense
<janrinze>
i really like how nextpnr makes ecp5 like the big brother of ice40 now :-)
<emily>
hm, how old is arachne-pnr? ~4 years too?
<daveshah>
Yeah, icestorm came first and arachne-pnr shortly after
<sorear>
What did we use pre arachne?
<janrinze>
daveshah: does nextpnr-ecp5 latch the output to I/O pins or do i have to do that explicitly?
<ZirconiumX>
whitequark: Managed to trigger yet another assert in FlowMap: ERROR: Assert `!lut_gates[breaking_lut].empty()' failed in passes/techmap/flowmap.cc:1273
<daveshah>
sorear: there was nothing, just tools to explore bitstreams
<daveshah>
janrinze: no, it doesn't pack output registers automatically yet
<daveshah>
If that's what you mean by latch?
<daveshah>
Currently the output registers aren't supported at all
<janrinze>
daveshah: Okay then I/O can have delay in respect to a global clock, right?
<daveshah>
Yes
<daveshah>
For now, a DDR primitive is the best bet
rohitksingh has quit [Ping timeout: 240 seconds]
<janrinze>
I see. I am running a 1024x786 VGA output and it is decent. when using a dithered image it shows somewhat.
<janrinze>
at almost 67 Hz refresh
<janrinze>
could also be the pll of course.
rohitksingh has joined #yosys
<janrinze>
daveshah: DSP 18x18 mult is not inferred yet, right?
<tpb>
Title: DSP inference for Xilinx (improved for ice40, initial support for ecp5) by eddiehung · Pull Request #1359 · YosysHQ/yosys · GitHub (at github.com)
<daveshah>
Yup, for all multiplies above a certain size
<janrinze>
I'll have a look at that.
<daveshah>
It's a pretty monstrous PR because it includes Xilinx and iCE40 stuff too
<daveshah>
The idea is about infrastructure for DSPs as much as anything else
<janrinze>
for up5k I didn't mind to use the primitives. it was a little confusing at first to get it right but it works very well.
<daveshah>
Yeah, when there are only 8 of them anyway instantiation isn't so bad
Jybz has quit [Quit: Konversation terminated!]
<janrinze>
Only needed one for this design.
<janrinze>
It does have one DSP MULT18x18 now. so it looks like it works.
<ZirconiumX>
After entirely too many attempts, I now have a "minimal" repro for the FlowMap assert bug
<ZirconiumX>
Well, *a* FlowMap assert bug
<ZirconiumX>
Given I turned up more in the process of finding this one
* ZirconiumX
updates Yosys, and it works fine
* ZirconiumX
sighs
<janrinze>
daveshah: true dual port ram might be necessary to manually infer?
<daveshah>
Yes, afraid so
<tnt>
it's not called infer if you do it manually :)
<janrinze>
i noticed how yosys was struggling :-)
<ZirconiumX>
Good news: bug still exists
<ZirconiumX>
Bad news: the test case I spent *hours* with bugpoint on doesn't trigger the bug in the current version