clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> I have used https://github.com/YosysHQ/nextpnr/blob/master/docs/constraints.md , why still "Warning: No clocks found in design" ?
<tpb> Title: nextpnr/constraints.md at master · YosysHQ/nextpnr · GitHub (at github.com)
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<janrinze> promach: do you have a clock?
<promach> janrinze: I have clk in my verilog
<janrinze> promach: is your verilog desing on github?
<janrinze> promach: might be easier to look at the verilog code and assess what the issue is.
<tpb> Title: Spidergon Networks On Chip · GitHub (at gist.github.com)
<janrinze> promach: datainput and dataoutput are missing in NoC module .. try adding like module NoC #(...) (clk,rest,data_input,data_output);
<janrinze> promach: if those are not driven nor used as output then Yosys can optimize them out and the result will be an empty design.
<promach> janrinze: No
<promach> NoC.v is used to encapsule the spidergon NoC
<promach> data_input and data_output need hardware pins if without NoC.v
<promach> do you understand what I mean ?
<janrinze> when you build with yosys, what is the 'top'?
<tpb> Title: Spidergon Networks On Chip · GitHub (at gist.github.com)
<promach> line 9
<janrinze> top=NoC thus no inputs for data_input and data_output
<janrinze> so if you add then to the module definition of NoC the accompanying pins will be retrieved from the constraints file.
<janrinze> the top module in your design only has clk and reset.
<promach> janrinze: there is no need for hardware IO pins for data_input and data_output
<promach> do you understand what I mean ?
<janrinze> then yosys will consider those irrelevant to the design and optimise out.
<janrinze> promach: how about you just try to add them as pins and then look at the result.
<janrinze> a design that is not connected can be optimized away. and thus no clock necessary either
<promach> janrinze: not enough hardware IO pins
<promach> on FPGA
<promach> janrinze: I just found some logic loop issues, let me solve those those first
<janrinze> promach: does not matter, you don't need to have real hardware to run yosys. the pin assignment only happens in nextpnr anyway.
<promach> yes, but data_input and data_output takes out too many IO pins
<promach> do you understand ?
<promach> not enough pins to assign, even inside nextpnr
<janrinze> hrmm.. how about creating a simple mux that is connected to io pins. then at least yosys can see that all input and output pins are used.
<promach> huh ?
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<janrinze> promach: you can try using "setattr -set keep 1" in the spidergon.ys file on line 8.
<janrinze> it might help keeping the design from being optimized away. and you cna then run nextpnr-ice40 to see if the design fits and what fmax is.
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<promach> janrinze: thanks, but I need to solve some logic loop issues first
<promach> that is more important now
* promach just solved those loop issues
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