clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<pepijndevos> For wide luts, can I recursively map to $lut, or should I hand code it all the way?
<pepijndevos> ECP5 has it hardcoded up to 7, but Gowin has 8-wide luts, so it'll be even more insane.
<daveshah> I would probably do it recursively
<daveshah> I think back when I did ecp5 there was a problem with recursive techmapping that's now fixed
<pepijndevos> cool, good to know
<daveshah> However, I wouldn't bother with wide LUTs without abc9
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<pepijndevos> why (not)?
<daveshah> The way Yosys calls it old ABC thinks a LUT4 and LUT8 have the same delay
<daveshah> This causes it to use way too many big LUTs hurting area
<pepijndevos> Hurting *area*? Or did you mean timing? Or both?
<daveshah> Area
<daveshah> Because abc thinks using large LUTs will be much better for delay (its primary objective as Yosys calls it)
<daveshah> than it actually is because the muxes add delay
<pepijndevos> Right... hmmm... will try it out a bit.
<daveshah> It would actually be possible to fix this by passing a LUT library in abc the same way as abc9
<daveshah> Just no one has bothered
<pepijndevos> Is there a nice way to make a N-wide LUT in verilog for testing?
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<pepijndevos> Great, abc deleted my code.
<ZirconiumX> pepijndevos: I think you could instantiate a $lut cell, and I believe they're of parametric width
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<pepijndevos> right
<ZirconiumX> daveshah: would abc9 still be superior to abc if you passed in a LUT library?
<pepijndevos> It's just a classic "you have a typo in a portname, but rather than warn you I'll delete your code"
<ZirconiumX> pepijndevos: `default_nettype none
<pepijndevos> ??
<ZirconiumX> Assuming you're working in Verilog here, anyway
<pepijndevos> Yea, VHDL yells at you for stuff like that
<pepijndevos> (I think at least... it just yells at you a lot more than Verilog, which I like)
<ZirconiumX> If you typo a parameter name, my understanding is that Verilog thinks you're declaring a new parameter that gets ignored
<ZirconiumX> And the old parameter stays at 'bx
<pepijndevos> ... which is *totally* what I want 99% of the time *facepalm*
<ZirconiumX> The fix is to tell Verilog not to think you're declaring a new parameter by using `default_nettype none
<ZirconiumX> As I understand it, anyway, daveshah or whitequark would know more about this than me
<whitequark> `default_nettype none is correct
<whitequark> you could also use read_verilog -noautowire
<mwk> wait, is it?
<mwk> for parameters?
<pepijndevos> So you just put that at the top of your file?
<ZirconiumX> Yep
<mwk> pepijndevos: yes
<mwk> every verilog file should have that line at the top
<pepijndevos> brb, making yosys PR
<whitequark> yes, Verilog also completely ignores unused parameters
<whitequark> well
<mwk> how helpful of it
<whitequark> it doesn't quite ignore them
<pepijndevos> echO "`default_nettype none" > hdr.v; find . -fname *.v -exec cat hdr.v
<whitequark> it's more that any parameters you define when instantiating a module take preference over the parameters you define when defining it*
<pepijndevos> (this is broken)
<whitequark> * unless you use localparam, in which case the *other* one gets ignored, I think
<whitequark> yep.
<mwk> aaaaaaaaaaaaaaaaaa
<whitequark> it also does some bizarre lazy evaluation thing
<whitequark> A parameter declared in a named block, task, or function can only be directly redefined using a defparam
<whitequark> statement. However, if the parameter value is dependent on a second parameter, then redefining the second
<whitequark> parameter will update the value of the first parameter as well (see 12.2.3).
<whitequark> I guess that makes sense?
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<ZirconiumX> pepijndevos: So how long is it until the Gowin flow uses VHDL techmap files? :P
* pepijndevos thinks
<pepijndevos> When yosys comes with VHDL support on by default.
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<ZirconiumX> So presumably when GHDL is rewritten in C?
<mwk> what is GHDL written in?
<ZirconiumX> Ada
<mwk> ...
<mwk> of course
<pepijndevos> There are a few others that are fairly complete, in Rust, Java, and Python
<pepijndevos> They are also just parsers, they don't do any synthesis and elaboration
<pepijndevos> Can't claim to understand this fully, but even integrating the Rust parser in Yosys would be a monumental effort I think.
<pepijndevos> Anyone know the correct vim fu for Yosys indentation?
<ZirconiumX> I'm not even sure Yosys is all that consistent with indentation
<ZirconiumX> pepijndevos: judging by the .editorconfig, probably :set ts=8 sts=8 noet
* pepijndevos install editorconfig vim plugin
<pepijndevos> This is a good idea
<pepijndevos> Oh no... the formatting was fucked up in some ways, and now it is fucked up in other ways :((((
<pepijndevos> fml
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<pepijndevos> I'm just going to cry now...
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