clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<somlo> fpga related article on LWN.net, mentioning yosys/trellis/nextpnr: https://lwn.net/SubscriberLink/801928/25775f5d4b1ec6c4
<tpb> Title: FPGAs and free software [LWN.net] (at lwn.net)
<whitequark> >One problem with the LUT-based mechanism is that it is slower than using a "real" gate as the MUXes are driven by a clock, so each level of MUX (e.g. two levels for the two-input XNOR) adds some delay.
<whitequark> um, what?
<sorear> addressed in the comments at least
<gruetzkopf> ehm, someone is confusing FFs with muxes?
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<chipb> bwidawsk: ^^^
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<bwidawsk> ugg
<bwidawsk> of all the times I present at XDC, lwn picks the one time I don't talk about graphics to make an article
<bwidawsk> hopefully at least it helped bring some eyes to the projects
<bwidawsk> even if I didn't have all the facts right
<chipb> I guess graphics aren't exotic enough to make the cut, huh?
<chipb> I thought your intro was a reasonable approximation. the audience for the most part are circuit consumers, not designers.
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<chipb> er, by my presumption, I mean.
<bwidawsk> yeah, I think also for the fake example I had, it was accurate
<bwidawsk> or close enough
<bwidawsk> perhaps I should have spent more effort to explain real FPGAs don't work like the example
<whitequark> a LUT is pretty much a 1-bit wide asynchronous SRAM, isn't it?
<bwidawsk> yeah, but the way I chained them up to make an n-LUT out of a 2-LUT
<bwidawsk> in my example
<whitequark> mhm
<whitequark> i'm still not sure where the clock comes from
<chipb> I took it more as a combinatorial logic delay tick moreso than a literal clock input to a FF.
<chipb> I guess I'd agree that the wording might've been more precise, but given I believe it was effectively a room full of laymen... *shrug*
<whitequark> it's just a pity, given the rest of the article is quite good
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