clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tnt> Does yosys have an option to just error out when a latch is inferred ?
<tnt> that's like 99.9% of the time an error in a fpga design ...
<pepijndevos> tnt select -assert-none t:$latch maybe?
<whitequark> there's read_verilog -nolatches
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<whitequark> which would result in a 'x
<tnt> Right, but that doesn't stop the build. I really just want it to crash.
<tnt> pepijndevos: I'll give that a shot.
<pepijndevos> When yosys tells me "Trying to prove $equiv for \gnt_1: failed.", does that mean it found an error, or just that it could not prove it?
<pepijndevos> And... any hints on finding the cause for this?
<pepijndevos> ERROR: Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).
<pepijndevos> I tried to whitebox and flatten the post-synthesis result
<pepijndevos> It seems flatten doesn't even have an -autoproc option
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<pepijndevos> I have no clue what is going on anymore. I think my simulation flip-flop models are subtly broken, but no clue what's going on
<mwk> tnt: it's going to be called $dlatch, not $latch
<mwk> and you need that assert after the proc pass, but before synthesis
<mwk> so it's rather unwieldy
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<whitequark> pepijndevos: I'm not sure if equiv works for latches, actually
<whitequark> er
<whitequark> wait, no, thread collision
<pepijndevos> hehe
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<janrinze> when building nextpnr without gui we don't need the huge chipdb binaries?
<ZirconiumX> janrinze: You still do
<ZirconiumX> Because the huge chipdb binaries contain all the routing information nextpnr needs
<janrinze> hmm. strange. I just built it now but the database files are nowhere to be found. Perhaps different names now?
<daveshah> That's because they are linked into the binary
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