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<Noname_Matt>
test.
<mwk>
toast.
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<matthuszagh>
hello. i'm having some trouble getting yosys to find verilog include files via a tcl script. I must be doing something obviously wrong but I can't pinpoint it. If I write the read_verilog line as 'read_verilog -sv -I/path... top.v' it works fine, but if I place the same string in an environment variable and read it out with $::env(INCLUDES) yosys emits an error saying it can't open the include file. I've checked that tcl gets the
<matthuszagh>
variable with puts $::env(INCLUDES) and it matches what I expect
<matthuszagh>
happy to post the actual scripts and output if that helps
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<Noname_Matt>
matthuszagh How are you calling yosys with the includes?
<Noname_Matt>
I ran into a (sort of) glitch in TCL like this
<Noname_Matt>
if you read it in like
<Noname_Matt>
set my_var "item1 item2 item3"
<Noname_Matt>
then call it like
<Noname_Matt>
exec "yosys" $my_var
<Noname_Matt>
you may get this problem as the three items are passed as one item with spaces in it
<Noname_Matt>
this is not a system() call. it's directly calling the exec() system call
<Noname_Matt>
the workaround is to do
<Noname_Matt>
eval exec "yosys" $my_var
<Noname_Matt>
which adds an extra level of evaluation which breaks apart the list
<Noname_Matt>
be careful about attacker controlled variable contents though, as this is adding an extra iteration of evaluation after all
<matthuszagh>
Noname_Matt: the way I call it is a bit different. I have a makefile with an export command at the top, then variable definitions then just yosys path/to/script.tcl
<matthuszagh>
i'm trying to come up with a minimal example that introduces, but so far it's working there...
<matthuszagh>
s/introduces/reproduces/
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<Noname_Matt>
ah, ok. I'm not familiar with yosys' internal TCL interfaces and interpreter
<matthuszagh>
thanks anyway!
<Noname_Matt>
though I have plenty of experience with synopsys' :P
<Noname_Matt>
need to learn more about yosys and the icestorm flow
<Noname_Matt>
I've only done some small proof of concept stuff so far
<matthuszagh>
ah was just about to ask if there's a way around the tcl usage (i.e. get a enviro variable from a yosys script) but i guess then you probably wouldn't know
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<Noname_Matt>
can you do something like
<Noname_Matt>
yosys --includes $includes
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<Guest4992>
argh. battery picked that exact instant to die
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<matthuszagh>
Noname_Matt: that doesn't appear to work either
<Noname_Matt>
It probably wouldn't. I was making up the command line option.
<Noname_Matt>
My point was rather can you have the calling makefile derefeence the variable?
<Noname_Matt>
dereference*
<matthuszagh>
oh yeak ok i see. unfortunately i don't think yosys has an include flag like that
<matthuszagh>
just via yosys -p
<matthuszagh>
I've filed a bug report, seems like it may be one
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<Noname_Matt>
anyone remember offhand what the maximum clock frequency of the RISCV core that can be implemented on the HX8K is?
<daveshah>
About 60MHz
<daveshah>
for both picorv32 and vexriscv
<daveshah>
70MHz might be doable with optimum config and good luck
<rvense>
how many clocks per instruction?
<daveshah>
picorv32 is around 3, vex is probably less than that
<tnt>
vex is also lower fmax though.
<tnt>
(at least on the up5k that's been my experience, for a minimal config)
<Noname_Matt>
Isn't the HX series a bit faster?
<daveshah>
Yes, but relative fmax would probably be simila
<Noname_Matt>
why is that?
<daveshah>
Because the up5k is roughly proportionally slower than the hx8k
<Noname_Matt>
I don't follow. If the HX series is faster (Wikipedia quotes 7.30 ns versus 9.00–9.36 ns which is around 25% improvement), wouldn't the maximum frequency for the core likewise be faster on one of the HX devices?
<daveshah>
Yes
<daveshah>
But it probably doesn't change picorv32 being higher fmax than vex
<Noname_Matt>
ah
<daveshah>
(idk what that wiki number is but the difference is more like 2-3x)
<Noname_Matt>
so would 60MHz be representative of the faster chips?
<daveshah>
Yes, that was in the context of an hx8k
<Noname_Matt>
so maybe 20-30MHz on other devices?
<daveshah>
Yeah
<daveshah>
tnt probably has more experience here
<tnt>
On the UP5k meeting 24 MHz with picorv is not too hard. I also have a design where it's at 30.72 MHz, but that one requires quite a bit of trying seeds to pass timing.
<tnt>
It can vary wildly depending on what you put on the memory bus obviously ...
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