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<lukego>
daveshah: thanks for the twitter thread link
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<FSM_Dude>
Hello!
<ZirconiumX>
Hiya
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<FSM_Dude>
I just synthesised a design and written it back to a verilog file using Yosys' `write_verilog` function. In the generated verilog file I see the selected cells from the cell library I used.
<FSM_Dude>
Would it be possible for me to create new cell with the same input and output as the selected cells, and then replace the selected cell with my new cell?
<ZirconiumX>
FSM_Dude: Depending on your requirements, techmap could do that
<FSM_Dude>
Okay, Ive written a TMR Flip Flop design in verilog. I'd like to synthesise that, and replace all Flip Flops in another design by those TMR Flip Flops
<ZirconiumX>
FSM_Dude: ...why did you have to bring up flip-flops?
<ZirconiumX>
They are amongst the most painful parts of Yosys at the moment
<FSM_Dude>
Im interested in the differences between using normal flips-flops vs TMR flip-flops
<ZirconiumX>
But yeah, you'd use techmap
<FSM_Dude>
Cool, Im gonna read some about `techmap`
<FSM_Dude>
Thanks a lot!
<ZirconiumX>
You'll want to use Yosys' internal documentation rather than the stuff on Clifford's website, as it's generally more up to date
<FSM_Dude>
Okay, I'll build the documentation then:) thanks again!
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<pepijndevos>
It seems that Yosys does not have a remainder operator, as present in VHDL. How does this work in Verific?
<pepijndevos>
Is that something that could be added?
<whitequark>
you probably want a new cell
<whitequark>
i imagine you want a new cell for division too
<whitequark>
(I assume VHDL uses quo/rem, in contrast to Verilog's div/mod)
<pepijndevos>
Why division? Are $div semantics diffrent than VHDL division?
<pepijndevos>
VHDL has both mod and rem operators
<whitequark>
hm
<whitequark>
try dividing by a negative number in both verilog and vhdl and compare the result
<pepijndevos>
I would not be surprised if Verilog is one of those cursed languages that has only modulus that is actually remainder but is still called modulus.
<whitequark>
hang on, i had a handy table somewhere
<pepijndevos>
whelp, I didn't actually remember which way Python % works... apparently *not* the same as verilog
<whitequark>
er, i'm wrong
<whitequark>
python's % is actually modulo
<whitequark>
the issue with division was something else, um
<pepijndevos>
Verilog % is sign of dividend, Python % is sign of divisor
<pepijndevos>
Yea, so python is modulo, verilog is remainder
<whitequark>
the sign of the result of division in python is xor of the signs of operands
<pepijndevos>
That's just... how math works, no?
<whitequark>
yes
<whitequark>
so i'm trying to remember where it doesn't match verilog
<whitequark>
there was something but i forgot :(
<pepijndevos>
divide by zero?
<whitequark>
no, nmigen defines that, so i emit a mux
<whitequark>
(x/0=0)
* pepijndevos
screams in math
<whitequark>
you'll be delighted that coq also defines division by zero to return zero
<whitequark>
and you can't really argue that it wasn't written by, well, mathematicians
<whitequark>
*to learn that
<whitequark>
for the same reasons too: it would be silly to return an Option<T> in that case, and using an exception wouldn't be good too, and you have perfectly good formal verification tools right in your toolkit
<whitequark>
oh of course
<whitequark>
Python division truncates towards -inf, Verilog division truncates towards zero
<pepijndevos>
ah yea i was about to suggest that
<whitequark>
which one does Verilog have?
<whitequark>
er
<whitequark>
VHDL
<pepijndevos>
I'm scared to look
<pepijndevos>
Probably the one Verilog doesn't have, leading to another bug
<ZirconiumX>
I just dragged out the VHDL 2008 spec
<ZirconiumX>
I can't into maths, so I'm hoping somebody can recognise it
<whitequark>
pepijndevos: it is a compile time error to use a signed number on the right hand side of % or // operator
<pepijndevos>
I see
<whitequark>
sometimes, the best way to deal with a hard problem is avoidance :)
<OK_b00m3r>
:)
<pepijndevos>
So only division by a constant?
<OK_b00m3r>
whitequark: may i OH that
<OK_b00m3r>
with ur nick
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<whitequark>
I guess?
<whitequark>
pepijndevos: no. nmigen has signed and unsigned values, which are separate types
<pepijndevos>
ah ofc
<whitequark>
(all values in nmigen have integer type with two properties: width and signedness)
<pepijndevos>
Okay, I think... VHDL does it the Verilog way, and round to zero
<pepijndevos>
ah wait...
<pepijndevos>
so confusing for my sleepy brain
<pepijndevos>
At least I'm pretty sure that equation ZirconiumX posted does not hold in Python
<pepijndevos>
Therefore I assume VHDL does the right thing (for DSP quantization error) and round to zero.
<pepijndevos>
Or not...
<pepijndevos>
Actually... well, never mind...
<whitequark>
hm, let's say A=-10, B=3, A rem B=-1, -10=(A/B)*3-1, A/B=-3
<whitequark>
that seems to imply round towards zero
<pepijndevos>
hurray
<pepijndevos>
Still thinking about the DSP part... I remember that some ADC designer truncated LSB rather than rounding properly, creating some horrible cross-over distortion. But I'm not awake enough to figure out which division scheme would be worse.
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