clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<hackerfoo> Where is the analysis implemented? Is it in ABC?
<hackerfoo> I've been working on bit-width inference for my compiler.
<hackerfoo> You can try it here with `:bo 8` then `:bc gcd`: http://hackerfoo.com/eval.html
<tpb> Title: popr (at hackerfoo.com)
<hackerfoo> Some of the calculations are trivial, like addition, but others take a while to figure out: https://github.com/HackerFoo/poprc/blob/master/primitive.c#L378-L423
<tpb> Title: poprc/primitive.c at master · HackerFoo/poprc · GitHub (at github.com)
<hackerfoo> There's a library, but I'd like to keep the code small: http://isl.gforge.inria.fr/
<tpb> Title: Index of / (at isl.gforge.inria.fr)
<hackerfoo> I suppose I'll end up adding a simplex solver eventually.
<hackerfoo> Oh, `:cv gcd` for Verilog, but it uses a lot of macros.
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<pepijndevos> wen installing prjtrellis and compilin nextpnr I get ModuleNotFoundError: No module named 'database'
<tpb> Title: GitHub - SymbiFlow/prjtrellis: Documenting the Lattice ECP5 bit-stream format. (at github.com)
<pepijndevos> guess I had to add -DTRELLIS_ROOT=/usr/share/trellis/
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<janrinze> does anyone know which standard is used for the two 'expansion' header connectors of the ecp5 evaluation board of lattice? I have been looking for boards that might fit on the connectors.
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<ZipCPU> pepijndevos: Did you init submodules? Does the prjtrellis/database directory have anything in it?
<ZipCPU> janrinze: Sorry, not me.
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<janrinze> https://github.com/trabucayre/fixFT2232_ecp5evn anyone have experience with this solution?
<tpb> Title: GitHub - trabucayre/fixFT2232_ecp5evn: Tool to fix FT2232s uart interface configuration for ecp5evn (LFE5UM5G-85F-EVN) board (at github.com)
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<janrinze> daveshah: any chance if the packing density branch will improve the speed of the design?
<daveshah> Unlikely
<daveshah> It doesn't change anything until utilisation is around 95%
<janrinze> daveshah: 95% utilisation on ecp5 is quite a design :D
<daveshah> Well, that is slice utilisation with loose packing so can be hit quickly with designs with lots of FFs
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<ZirconiumX> A LiteX SoC capable of running Linux can max out a -45F pretty easily
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<daveshah> Only with Rocket - Vexriscv shouldn't be anywhere near that close
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