clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> Have anyone used https://github.com/FPGAwars/apio before ?
<tpb> Title: GitHub - FPGAwars/apio: Open source ecosystem for open FPGA boards (at github.com)
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<pepijndevos> welp Warning: Failed to find a route for arc 20 of net clk.
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<whitequark> janrinze: yosys does not currently have TDP RAM support
<whitequark> inference support*
<pepijndevos> I probably have a typo or a missing pip somewhere, I think??
<pepijndevos> (using the generic backend to PnR stuff)
<pepijndevos> It seems somehow that the clock wire doesn't have the right pips to connect all the way.
<daveshah> There are some ifdefs in the router you can enable (combined with --debug) to see what it is trying
<pepijndevos> Oh ok, I'll have a look
<pepijndevos> Is there also a way to dump the internal routing graph? I suppose it might be a bit big to comprehend
<daveshah> No, although in the past I've usually used python scripts to poke the routing graph
<pepijndevos> daveshah, can you somehow get an interactive console into nextpnr, or you have to write the poking in --pre-pack over and over?
<daveshah> the only interactive console is in the gui
<daveshah> code.interact() in a script might also work
<daveshah> But I haven't tried the latter
<pepijndevos> Hm, does the gui work with generic?
<pepijndevos> I tried good old pdb.set_trace() but that just hangs without getting a prompt
<daveshah> Just tried and code.interact() seems to work
<daveshah> Not sure about gui, I think there were some issues with the generic prepack scripts
<pepijndevos> Where do you put that? NameError: name 'code' is not defined
<daveshah> need an import code too
<daveshah> something is needed for ctx to work properly too; let me see
<daveshah> so these two lines are what you want
<daveshah> import code
<daveshah> code.interact(local=locals())
<pepijndevos> btw, this is the output with --debug, have not looked into it much further https://paste.ubuntu.com/p/K8mqCHr77J/
<tpb> Title: Ubuntu Pastebin (at paste.ubuntu.com)
<daveshah> For routing graph debugging you probably want to uncomment some of the ifdefs in the router too to see what it visits along the way
<pepijndevos> yea, will do that after I'm done poking at the Python api
<promach> how do I create a pcf pins (clock and reset) declaration file for ice40 architecture ?
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<tpb> Title: nextpnr/ice40.md at master · YosysHQ/nextpnr · GitHub (at github.com)
<tpb> Title: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at github.com)
<promach> thanks daveshah
<pepijndevos> Yea, seems like there is no pip on the IOB output -.-
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<daveshah> That would make sense
<daveshah> It might be to do with IOLOGIC (input registers etc), needing to be routed through
<pepijndevos> IIIINteresting... The IOB is connected to Q6, but a logic tile only has Q0-Q5 so my normal loop just doesn't make the right pip
<daveshah> At a guess, non-logic interconnect tiles have the extra Q6-7
<daveshah> I wouldn't be surprised if things like BRAM needed those extra signals too
<pepijndevos> Probably. But it also means the muxes just have different options at these locations. So I need to go back and figure that out.
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* pepijndevos pokes
<ZirconiumX> Thanks Pepijn
<pepijndevos> Although 4 days seems... not that much
<pepijndevos> Maybe he'll see my poke in 4 days ;)
<ZirconiumX> Sure, but email is rather opaque for this :P
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<promach> Do anyone have pcf examples for tinyfpga similar to https://github.com/icebreaker-fpga/icebreaker-examples/blob/master/icebreaker.pcf ?
<tpb> Title: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at github.com)
<tpb> Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com)
<promach> thanks daveshah
<promach> ERROR: package does not have a pin named 'B2' (on line 94) ???
<tpb> Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com)
<daveshah> Are you passing --package to nextpnr
<promach> what do you mean ? I am using GUI
<daveshah> Are you choosing the right package?
<promach> daveshah is it bg121 ?
<daveshah> No, I think it is cm81
<promach> cm81 or cm81:4k ?
<promach> for tinyfpga BX
<daveshah> cm81
<promach> daveshah why is my json file https://github.com/promach/noc/blob/master/spidergon.ys#L9 is for hx1k ?
<tpb> Title: noc/spidergon.ys at master · promach/noc · GitHub (at github.com)
<daveshah> The json file doesn't contain a device
<promach> once I open the JSON file, the GUI switch my choice from hx8k to hx1k
<daveshah> I'm not sure why that is hapenning
<promach> synth_ice40 -flatten -top NoC -json spidergon.json
<promach> is this command correctly ?
<daveshah> Yes
<daveshah> It sounds like the problem is on the iCE40 side
<promach> did I miss anything tinyfpga-specific parameters ?
<daveshah> Try doing it on the command line nextpnr-ice40 --lp8k --json spidergon.json --package cm81 --gui
<promach> you forgot pin.pcf
<daveshah> oops
<promach> daveshah usually which IO port is used for reset ?
<promach> for tinyfpga BX ?
<tpb> Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com)
<daveshah> Any of the pins
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<promach> daveshah Warning: No clocks found in design
<daveshah> Sounds like you don't have any registered timing paths
<promach> I do not understand. I have so many always @(posedge clk)
<daveshah> Are there flip flops in the synthesis statistics?
<daveshah> they might be being optimised away
<promach> daveshah is the no clock warning because of https://github.com/promach/noc/blob/master/spidergon.ys#L11 ?
<tpb> Title: noc/spidergon.ys at master · promach/noc · GitHub (at github.com)
<daveshah> No, because that doesn't remove any flops nor does it touch the JSON file that synth_ice40 previously created
<promach> daveshah then what causes the no clock warning ?
<daveshah> are there the right number (roughly) of SB_DFFs in the log output of synth_ice40
<promach> what log output ?
<daveshah> it sounds a lot like your flipflops are being optimised out
<daveshah> Yosys' log output
<daveshah> It looks like your NoC module has only inputs
<daveshah> That means all the remaining logic will be optimised away
<promach> and ?
<promach> you mean NoC.v
<promach> ?
<promach> daveshah
<daveshah> yes
<daveshah> that is your top module, right?
<promach> yeah
<promach> daveshah so, there is nothing wrong for "Warning: No clocks found in design" ?
<promach> and I do not need to fix anything ?
<daveshah> Well, your design is empty
<promach> empty ? what do you mean ?
<daveshah> There is no logic in your design
<promach> ????
<promach> what ?!
<daveshah> It's a circuit with only inputs
<promach> so, the warning will go away once I add output ?
<daveshah> Yes, because then there will be some logic left
<daveshah> so long as that output depends on some clocked logic
<promach> ok
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<pepijndevos> I'm still messed up with DFF naming
<pepijndevos> _DFFE_PP_ is positive clock, positive reset, right?
<pepijndevos> I mean... positive enable
<daveshah> positive clock, positive enable, no set/reset
<pepijndevos> right
<pepijndevos> __DFFS_PN0_ is positive clock negative reset, reset to zero?
<daveshah> yes, active low sync reset to zero
<pepijndevos> and __DFFNSE_PN0 is... is it now the reset or the enablet that is negative?
<daveshah> reset
<daveshah> negative enables aren't really well supported
<daveshah> (dff2dffe doesn't map them, idk why there is even a primitive for them)
<pepijndevos> So once you have a reset, negative enable is just not a thing
<pepijndevos> Yea, that fixed it..
<pepijndevos> ty
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