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<lukego>
Is there any Emacs mode that vaguely suits rtlil?
<ZirconiumX>
Oh, hey lukego
<lukego>
G'day ZirconiumX :)
<ZirconiumX>
RTLIL is not really intended for human editing
<lukego>
I'm mostly intending to read at the moment. I think a little syntax colouring would help to make the \src attributes less distracting for example.
<ZirconiumX>
I mean, you can always write one :P
<lukego>
Sure just curious first what other people are doing e.g. maybe some generic commands can do the job too. Just now I'm using 'grep -v' but that's clunky :)
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<lukego>
Seems like the yosys package for nixpkgs doesn't pull in the runtime dependencies needed for 'yosys show'. I wonder if it should.
<ZirconiumX>
cc emily, maybe?
<lukego>
Good entry point for me into Yosys, checking for how it finds those commands.
<lukego>
via PATH by the look of it. So I guess the nix package would need a wrapper script.
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<whitequark>
daveshah: btw, have you ever considered porting some ecp5-only features of nextpnr back to ice40?
<daveshah>
I think it's only out-of-context that is ecp5 specific
<daveshah>
I will when I get round to it
<daveshah>
(and I wanted to deal with a few other related things first)
<whitequark>
oh alright, I somehow misremembered that there's more
<whitequark>
related: what about making HeAP the default on iCE40?
<daveshah>
Also on the TODO list (need to fix an edge case of a design with no regular IO, just oscillator and RGB primitives, causing a singular matrix)
<whitequark>
gotcha, thanks!
<daveshah>
I better get the iCE40 stuff into shape before the rumoured iCE28 or whatever is announced next month...
<whitequark>
the what
<whitequark>
i thought lattice gave up on that series
<daveshah>
Oh it is only the spiritual successor
<daveshah>
I don't think it will actually be called iCE28
<daveshah>
But it will be a similar low power/feature set to the UltraPlus
<ZirconiumX>
I just hope their product naming scheme is better than their primitive naming scheme
<daveshah>
Primitive naming will doubtless be similar to ECP5
<whitequark>
what about the CLBs?
<daveshah>
At a guess roughly ECP5-like, although I've heard some possible further experimentation has gone on
<daveshah>
The only thing they've officially said is still LUT4 based
<whitequark>
ah hm
<whitequark>
so they basically put the ice40 logic into trash?
<daveshah>
Yeah definitely
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<daveshah>
By the UltraPlus you could tell they were really hacking at the designs with no real understanding of them
<daveshah>
All the SiliconBlue people left soon after the merger, afaik
<daveshah>
Indeed Radiant tries to make the iCE40 logic look more like ECP5, presumably to fit the Lattice CAD architecture (e.g. rotating the chip through 90degrees)
<ZirconiumX>
So we're expecting this to be essentially a low-power ECP5-like?
<daveshah>
Yes
<daveshah>
I believe with iCE40UP-style large RAM blocks too (not sure if still single-ported)
<ZirconiumX>
That's...actually interesting to look at
<ZirconiumX>
"100% Focus on FPGA"
<ZirconiumX>
But isn't MachXO3 a CPLD?
<daveshah>
No, it's an FPGA
<daveshah>
Anything with LUTs is an FPGA, imo
<ZirconiumX>
Right, okay
<whitequark>
oh, so you would call LUT-based arches "FPGA" and SOP-based "CPLD"? that's one way to do it
<whitequark>
re SB people leaving: interesting. was their HDL/layout so impenetrable that the Lattice people couldn't figure it out?
<whitequark>
or is it just hard?
<daveshah>
My guess is that something like an FPGA is always going to be pretty nasty, because a lot is manually laid out rather than HDL
<daveshah>
It was also doubtless rushed given the constraints on SiliconBlue
<daveshah>
In fact I think SB would have gone bankrupt were it not for Lattice
<daveshah>
To get you an idea of the bodgniness - the DSPs are interconnected through a hacked logic tile
<whitequark>
I recall some of that I think
<daveshah>
Said logic tile still has all the logic intact - but the tools always setting the LUT as a route through from cascade in to out
<daveshah>
The DSP then taps of the LUT inputs and feeds its output into the logic tile cascade path
<daveshah>
Where the LUT then feeds it back to fabric
<daveshah>
If they knew what they were doing then they definitely wouldn't have left the redundant LUT in place adding delay but just kept the interconnect part of the tile
<whitequark>
wait what
<whitequark>
the ... LUTs are there
<whitequark>
lmao
<daveshah>
Yes
<whitequark>
what the fuck
<whitequark>
that's amazing
<daveshah>
I think the FFs might be there too but I've never tested
<whitequark>
this is webdev-level quality
<daveshah>
The lm4k goes a different approach and connects its hard IP via complete IO tiles
<daveshah>
Almost as if they laid two chips out next to each other and added some wires between the two
<whitequark>
um
<mwk>
they what
<daveshah>
If they weren't in wafer level packaging I'd be putting them in an xray
<daveshah>
But it must be one die, just laid out as two
<whitequark>
can someone send me some so i can take die shots
<mwk>
can... can you actually usefully program the LUT in any way?
<whitequark>
at least they didn't use the logic tile FF as DSP output register
<daveshah>
I think you could use the LUT just as a LUT if you were running low
<daveshah>
Just without the cascade function
<whitequark>
would be fun to make nextpnr do that
<daveshah>
Yeah, I might have a play with that
<whitequark>
hm, can't buy lm4k locally :/
<ZirconiumX>
(could somebody expand lm4k for me?)
<mwk>
ZirconiumX: one of the ice40 parts
<daveshah>
lm1k and lm2k are the same dice btw
<daveshah>
as lm4k
<whitequark>
lp4k is a different device right
<ZirconiumX>
Ah, I see
<daveshah>
lp4k is rebranded lp8k
<daveshah>
One of the classic parts
<whitequark>
um
<whitequark>
ice5lp4k?
<daveshah>
Oh that's the iCE40 ultra
<whitequark>
NOT CONFUSING AT ALL
<daveshah>
idek where the 5 comes from
<daveshah>
I don't think it's 5nm
<daveshah>
And then they went back to 40 for ultralite and ultraplus
<whitequark>
ultralite is um. lm4k?
<daveshah>
No, ice40ul1k
<whitequark>
what the hell
<whitequark>
how many of these models do they -have-
<daveshah>
lm4k is a really weird somewhat abandoned series between the lp/hx and the various ultra parts
<daveshah>
It is not surprising its hard to get hold of
<daveshah>
The official dev board is also ridiculously expensive for some reason
<whitequark>
when did they rebrand UP as "low power AI"
<daveshah>
It's their whole new strategy
<daveshah>
"edge AI"
<daveshah>
They've got some model compiler tool now too, sensAI
<whitequark>
also what's up with having both diamond and radiant
<daveshah>
Radiant is an attempt at a fresh start
<whitequark>
ah, without neocad stuff
<whitequark>
but... it can only do UP?
<daveshah>
Oh no still neocad inside
<daveshah>
At least to some extent
<whitequark>
oh.
<daveshah>
Just a new GUI and some supposed pnr improvements
<daveshah>
Also some kind of IP integrator that doesn't quite work yet
<daveshah>
Radiant will be the CAD tool for new archs going forward
<daveshah>
The up5k is really just a proof of concept for it
<whitequark>
oic
<ZirconiumX>
Is Radiant a front-end to the old Diamond toolchain, or from-scratch?
<daveshah>
Half and half
<daveshah>
They've supposedly improved things a bit and changed the design database format
<daveshah>
But there's still plenty of NeoCAD in thete
<daveshah>
Unlike Vivado which was a near total from scratch job afaik
<whitequark>
"1000 person years"
<dh73>
I know two folks that worked at Xilinx when they started to develop Vivado. They said that, a lot of departments got really crazy deadlines, and lots of engineering burnout
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<daveshah>
Oh another funny Radiant thing is that it is at least trying to replace some Tcl with Python (in particular the core generators) - but in true EDA style, Python 2.7
<daveshah>
Yay for building using a dependency that will be obsolete by the time your tool is actually properly launched
<whitequark>
lol
<whitequark>
I'm actually not sure if I dislike Tcl that much
<whitequark>
in particular, it's very lightweight, unlike Python
<whitequark>
I would gladly use Tcl in nextpnr, because right now I assume I can't rely on any scripting capability at all
<daveshah>
Yeah, Python makes things for stuff like describing FPGAs or more complex prototyping
<daveshah>
It's a shame linking it is such a nuisance
<whitequark>
do you think there's any chance nextpnr could gain tcl bindings?
<whitequark>
I might volunteer to provide the implementation there
<whitequark>
after some in-depth Vivado work I grew to appreciate its Tcl capabilities
<daveshah>
I'd really rather not have to maintain two sets of bindings
<daveshah>
Another possibility is micropython
<dnotq>
Did you actually like Tcl though, or is the appreciation because it allowed you to do something you otherwise could not?
<daveshah>
Although it wouldn't work out of the box with Boost because it doesn't implement the CPython API
<dnotq>
Was Lua considered? It is designed to be embedded, is fast and lightweight. At work I have to maintain a code-base that binds Python and it is a PITA.
<ZirconiumX>
The Lua C API is mildly terrifying
<ZirconiumX>
setjmp/longjmp error handling
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