clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> piegames1: Welcome to the channel!
<ZipCPU> Let me take a peek at that line ...
<ZipCPU> Ahh, yes ... the reset within the faxil_slave works off of a *synchronous* reset
<ZipCPU> As a result, if the reset is asserted on a given cycle, the VALID must be low on the *following* cycle
<ZipCPU> As for asynchronous resets, anything asynchronous requires a synchronizer at the end of it. That means that a single clock cycle asynchronous reset isn't going to happen
<ZipCPU> piegames1: Another thing to remember, according to spec you cannot have a combinational path between AXI inputs and outputs. That means everything must be registered. Registering the xVALID signals requires that it takes a clock to respond to a reset.
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<piegames1> zipcpu, thanks and thanks. With the rule about "no combinatorial paths" I did not think of the reset as "input", but it kind of makes sense
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<finnb> Is there a place to talk about open source firmware in general?
<whitequark> what kind of firmware?
<finnb> FPGA firmware
<finnb> any kind
<whitequark> ##openfpga maybe
<finnb> Thanks :)
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