<meawoppl>
followup, is bitrange assigment like this legit
<meawoppl>
reg[15:0] foo;
<meawoppl>
posedge @(whatever)
<meawoppl>
foo[15:8] <= foo[7:0];
<meawoppl>
?
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<ZipCPU>
meowppl: Yes, that's a legitimate assignment. I like to place the assignment to foo[7:0] nearby, but it can be done in a separate block
<ZipCPU>
(Verilator might have problems with separate blocks for separate parts of a value, but it is legal Verilog)
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<Xiretza>
I can't get synth_xilinx to infer true dual port RAMs (two read and write ports, one of each per clock domain), is that simply not supported yet?
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<whitequark>
yes
<whitequark>
yosys can't do TDP RAM at all yet
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<Xiretza>
ooooh, I see, that explains it. I guess it was never necessary for ICE40/ECP5
<daveshah>
It is necessary for ECP5
<daveshah>
It's just memory_bram is too horrible for anyone to have attempted to do it yet
<Xiretza>
that doesn't exactly inspire confidence in trying it myself... to be clear, most configurations with just a single clock domain should be possible, just not two independent clocks per $mem?
<mwk>
Xiretza: no
<mwk>
the problem is that yosys doesn't know how to merge a single port in both read and write modes
<mwk>
*how to use
<mwk>
so if you read from memory in one place, and write to it in another place, it has to use two different ports
<Xiretza>
mwk: and yosys only supports a single port per memory?
<mwk>
no
<mwk>
it supports however many ports are available
<mwk>
just every available port can only be either read or write, not both at once
<Xiretza>
mwk: okay, and how do those relate to clock domains? do all ports have to be on the same clock?
<mwk>
clock domains don't matter, it's about ports
<mwk>
the two ports can be on two different clocks, and yosys does support that
<Xiretza>
so it can only use each of the two ports a RAMB36E1 offers as either read or write (so read+read, read+write, or write+write, only one of which makes sense)?
<mwk>
correct
<daveshah>
read-read would make sense for a ROM
<daveshah>
but it's not supported
<mwk>
huh, it's not?
<daveshah>
I don't think so, it would need an extra rule for memory_bram
<mwk>
ugghh
<mwk>
right
<mwk>
of course
<daveshah>
memory_bram itself should support such a pattern
<Xiretza>
daveshah: right, are those built from RAMB36E1 though?
<daveshah>
but the rules and techmaps don't
<daveshah>
Xiretza: yes or RAMB18E1 for smaller ones
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<Xiretza>
interesting, for some reason I thought there were separate ROM blocks. alright then, seems like some more in-depth work is required, don't think I have much of a chance to take that on. I'll just keep the designs I'm testing to two ports for now
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<mwk>
ROM is just preinitialized RAM with the ports used only for read
<Xiretza>
yeah, it makes sense now that I think about it, just never occured to me
<Xiretza>
thanks a lot for all your help!
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