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<corecode>
janrinze: why overpriced? somebody had to design it, pay for parts, keep them in stock, etc.
<corecode>
i just noticed that coming out of programming, my design thinks that there is a new SPI transaction happening, but it is just the programming signals still being active
<corecode>
i wonder how to deal with that
<whitequark>
add a reset
<corecode>
i have a reset
<whitequark>
not long enough?
<corecode>
hm, maybe my spi peripheral doesn't use the reset
<corecode>
i guess i'm just using CS as reset there
<corecode>
different clock domain, etc.
<corecode>
yea i guess that's it
<corecode>
thanks
<whitequark>
np :)
<whitequark>
glad to be your rubber ducky
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<corecode>
well no, the reset was a good point
<corecode>
how does that even work, two reset signals
<whitequark>
evidently it doesn't?
<whitequark>
or do you mean you want two resets and asking how to do it?
<corecode>
so my spi input circuit uses CS as active low reset
<corecode>
but that means that this circuit will be active even while the rest of the design is in reset
<whitequark>
is the SPI block clocked by SPI clock or system clock?
<whitequark>
(I assume that's an asynchronous reset)
<corecode>
yes it is clocked by SPI clock
<corecode>
ah interesting, i use rising CS as reset
<whitequark>
do you have CDC between the SPI block and the rest of the circuit?
<corecode>
yes i do
<corecode>
for whole bytes and associated signals
<whitequark>
hmmm
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