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<mkurc>
ZirconiumX: The solution that you suggested 'assign reset_val = (input_reset === 1'b0) ? 1'b0 : 1'b1' is not suitable for me. If I write such a statement in the techmap then it makes Yosys infer $mux cell.
<mkurc>
ZirconiumX: I need a way to determine whether a signal is unconnected inside a generate statement. The condition has to be constant during synthesis.
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<ZirconiumX>
mkurc: But as far as I can tell, Yosys can't do that at present, presumably because nobody thought you'd need to check for a port being disconnected.
<whitequark>
I think there is
<whitequark>
_TECHMAP_CONST{MSK,VAL}_ and _TECHMAP_CONNMAP_<PORT>_ can do this, no?
<whitequark>
of course, it's yosys-specific
<ZirconiumX>
We tried that
<whitequark>
ah
<ZirconiumX>
Actually, not CONNMAP.
<ZirconiumX>
Maybe worth trying that, mkurc
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<daveshah>
Verilog does support default port values (eg input wire rst = 1'b1)
<daveshah>
But I don't know if this works with techmap
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<develonepi3>
mmicko Have you used Yocto? I have a Ubuntu system builds rpi4 which creates deb packages and rpi4-64 which creates rpm package. This appears to be a pretty good feature. Now if you I can just get nextpnr, yosys, and arachne-pnr to build. Yosys compiles but is getting a QA error Unable to recognise the format on yosys. Nextpnr I need to learn how to execute cmake -DARCH=ice40 . in a recipe. Makefiles just use oe_runmake.
<develonepi3>
mmicko I now have icestorm_0.1+git0+041c075e4a-r0_armhf.deb or icestorm-0.1+git0+041c075e4a-r0.aarch64.rpm
<develonepi3>
mmicko arachne-pnr I need to fix the use of sum which is in the Makefile. The sum which is in coreutils & busybox.
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<meawoppl>
heyo heyo
<meawoppl>
I have another small issue to report
<meawoppl>
*two small issues
<meawoppl>
I think using yosys as a total n00b to verilog has help me turn up the weird
<meawoppl>
bug #1:
<meawoppl>
bus assignment is ignored in weird ways:
<meawoppl>
`thing[7:0] <= otherThing[7:0];`
<meawoppl>
bug #2:
<meawoppl>
my IDE automatically adds:
<meawoppl>
`endmodule : ModuleName` which yosys seems to dislike...
<meawoppl>
vs. just `endmodule`
<daveshah>
Not sure about #2, I'd have to check the standard. Can you explain #1 better?
<meawoppl>
yeah, there are a bunch of permutations that seem to be quietly ignored:
<meawoppl>
so I think the vaslid way to do this is w/o the array notation:
<meawoppl>
`thing <= otherThing[7:0];` Which seems to work as expected
<meawoppl>
`thing <= otherThing[0:7];` is ignored (no bus endian swap?)
<meawoppl>
I am not sure which are/are not legal
* ZirconiumX
is very glad they're not a language lawyer who has to deal with these kinds of questions
<daveshah>
I don't think that does a bus endian swap
<meawoppl>
I think it isn't valid honestly, but it does get treated somehow strangly under the hood vs. a raised syntax exception or similar
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