clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> Are parameter names in Verilog case-sensitive? I'm assuming so, but it doesn't hurt to check.
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<ZipCPU> ZirconiumX: Yes. All identifiers in Verilog are case-sensitive
<ZirconiumX> So what am I meant to do about Quartus primitives where the parameters are not case-sensitive?
<ZipCPU> That said, if you dare to use lowercase letters in your parameter names, you'll be using what's known as "Heathen Verilog". :p
<ZipCPU> You mean ... Quartus is broken?
<ZirconiumX> Why does this surprise you?
<ZipCPU> Sigh
<ZipCPU> Yosys isn't broken ;)
<ZipCPU> With some hardware, the MAX10 for example, you can go from Yosys to Quartus with an EDIF file
<ZirconiumX> But yeah, altsyncram #(.OpErAtIoN_mOdE("dual_port"), ...) is accepted by Quartus
<ZipCPU> ... or was it a VQM file? I documented it in the first article on the MAX1000
<ZirconiumX> VQM.
<ZirconiumX> Or at least that's what I currently emit
<ZipCPU> IIUC, the problem is that VHDL isn't case-sensitive
<ZirconiumX> EDIF appears to have been dropped in recent-ish Quartus versions? Or at least squirreled away out of sight from documentation
<ZipCPU> So it might be a cross-language issue .... ??
<ZirconiumX> Hurray.
<ZirconiumX> /s
<ZipCPU> /s ?
<ZirconiumX> This is going to require some fun `attrmap` calls
<ZirconiumX> /s means sarcasm.
<ZipCPU> Ah
<ZirconiumX> Maybe it's a bit of personal preference, but SCREAMING CAPS LOCK IS A BIT DIFFICULT FOR ME TO READ
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<whitequark> ZipCPU: ZirconiumX: Yosys has `attrmap -tocase` for this specific issue
<ZipCPU> ^ +1. Thanks!
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<develonepi3> hi all: I just cross-compiled icestorm & arachne-pnr on a Ubuntu 16.04 for a RPi, using the yocto sdk. See "https://github.com/develone/raspberrypi2_yocto-zeus/blob/master/docpi4/icestor-arachne-pnr-CC.pdf" & "https://github.com/develone/raspberrypi2_yocto-zeus/blob/master/docpi4/testing_cross_compile.txt". I tested creating a catzip.bin from catzip.blif & catzip.pcb. I tested the catzip.bin on my catboard, it worked okay. The next steps
<develonepi3> will be to cross compile yosys & nextpnr.
<ZirconiumX> Yeah, you really shouldn't use arachne-pnr anymore.
<develonepi3> Zirconiumx I understand, this was just testing the cross compile sdk, which uses "make -e" to override the environment variables with sdk variables..
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<janrinze> Is SPRAM still not yet inferred by yosys for up5k?
<daveshah> Afraid not, yosys still has no support for combined readwrite ports
<janrinze> daveshah: that's a bummer.. Okay, so I will need to do it manually.
<janrinze> Already wondered why i had the bootloader code in my old up5k stuff
<janrinze> Is there a tool to setup spram similar to readmemh ? would be helpful.
<daveshah> No, SPRAM is not initialisable
<janrinze> okay, then it makes sense.
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